Analog Design & Layout Engineer

The MOSIS 2.0 PIES Team is Hiring

Background: The California Defense Ready Electronics and Microdevices Superhub (California DREAMS) will promote innovation and lab-to-fab transition for RF and other technologies in the Southern California region. MOSIS 2.0 will play a critical role in providing access to university nanofabs and industry prototyping and production fabs in support of rapid prototyping for Government- and Industry-funded R&D projects. The primary end uses for the service span from advanced RF-spectrum communications and sensing applications such as 5G/6G and related domains to advanced digital design. The Prototype Integration and Engineering Services (PIES) team will operate within MOSIS 2.0 to provide engineering support for users bridging the valley between innovations and production.

This role seeks a skilled engineer who excels in one or more of the following: analog circuit/RF design, digital circuit design, and physical layout implementation. The successful candidate will work directly with MOSIS 2.0 customers to help design and layout circuits across a range of process technologies. Additionally, they will support USC's tape out classes and contribute to funded research projects within the ECE department. This is an ideal opportunity for someone who enjoys blending hands-on technical work with educational and research support.

Location:
California (On-site at USC/ISI in Marina del Rey, and at the University Park Campus)

Position Type:
Full-Time, Research/Support Role, MOSIS 2.0 (California DREAMS Microelectronics Commons) / ECE Department.

Responsibilities:

• Customer and Project Support:
  • Collaborate with MOSIS 2.0 customers to develop high-quality analog circuit designs or digital circuit designs and assist customers with layout implementation.
  • Provide technical guidance on best practices for schematic capture, simulation, layout creation, and design rule compliance across various process technologies (e.g., CMOS, BiCMOS, III-V).
• Academic and Research Engagement:
  • Assist in the delivery of tape out classes at by demonstrating layout techniques and troubleshooting common design issues.
  • Support funded research projects by providing design and layout expertise, including post-layout simulation, parasitic extraction, and layout verification.
• Technical Documentation and Collaboration:
  • Prepare detailed design reports, layout closure documentation, and technical presentations for both industry and academic stakeholders.
  • Collaborate with faculty, students, and industry partners to continuously improve design methodologies and workflows.

Qualifications:

• Educational Background:
  • Bachelor's, Master's degree, or PhD in Electrical Engineering, Electronics, or a related field
• Technical Expertise:
  • Minimum 3 years of experience in analog circuit design and/or analog layout.
  • Proficient in industry-standard CAD tools (e.g., Cadence Virtuoso, SPICE simulators, Mentor Graphics tools, or equivalent).
  • Strong understanding of layout verification methods (DRC, LVS) and parasitic extraction techniques.
  • Experience with device, electromagnetic, or photonic component simulations desired but not required.
• Interpersonal and Communication Skills:
  • Excellent communication skills with the ability to work effectively with customers and academic teams.
  • Prior teaching, tutoring, or workshop facilitation experience is a plus.
• Adaptability:
  • Ability to work across multiple process technologies and adapt designs to meet various manufacturing guidelines.

The annual base salary range for this position is $153,012 - $180,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate's work experience, education/training, key skills, internal peer equity, federal, state and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations.

Minimum Education: Bachelor's degree Addtional Education Requirements Combined experience/education as substitute for minimum education Minimum Experience: 5 years Minimum Skills: Thorough knowledge of device physics and VLSI electrical engineering principles at the device and circuit level. Working knowledge of electronic semiconductor test equipment, CAD tools, and other engineering software tools.