Overview
Skills
Job Details
Role Title: ASIC/RTL Design Engineer - Senior
Location: Santa Clara, CA / Longmont, Colorado (Onsite/Hybrid)
Duration: 12+ months contract
DESCRIPTION:
Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.
Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows
Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
Constantly review/identify the places to improve the process and ways to identify the issues early in the design phase.
PREFERRED EXPERIENCE:
Worked with EDA tools that enable RTL quality checks
Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
Experience with analyzing the timing reports and identifying both the design and constraints related issues.
Ability to multitask, grasp new flows/tools/ideas
Experience in improving the methodologies.
Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.