ASIC / SoC Design Engineer

ASIC/Soc Design
Location: Irvine, CA

Position Summary:
ASIC / SoC Design Engineer to contribute to the development of advanced memory subsystem controllers and interface technologies. In this role, you will work from high-level architectural specifications to define microarchitectures, implement RTL, integrate third-party IPs, and deliver PPA-optimized ASIC/SoC designs through to tape-out.

Key Responsibilities:

• Translate architectural specifications into block-level microarchitecture with a focus on power, performance, and area (PPA) optimization
• Develop synthesizable RTL in Verilog or SystemVerilog for custom controller, interface, and logic modules
• Integrate and validate third-party IP cores including PCIe, CXL, DDR3/4/5, NAND, and SSD-related interfaces
• Perform functional simulations, unit-level verification, and assertion-based checks
• Execute logic synthesis, static timing analysis (STA), clock domain crossing (CDC) checks, and timing closure
• Collaborate across hardware, firmware, validation, and physical design teams to drive full-chip integration
• Support bring-up and post-silicon validation of ASICs and FPGA prototypes
• Contribute to design reviews, documentation, and test planning

Required Qualifications:

• BS in Electrical or Computer Engineering with 10+ years of relevant design experience, or
  MS with 8+ years in ASIC / SoC hardware development
• Demonstrated expertise in PCIe, CXL, DDR3/DDR4/DDR5, NAND flash, and SSD controller design
• Solid understanding of RTL design, digital logic principles, and ASIC/SoC development flows
• Proficient in EDA tools for synthesis, STA, and CDC analysis
• Experience integrating and validating commercial IP blocks in complex SoC environments
• Strong debugging, problem-solving, and analytical skills
• Excellent communication and documentation abilities

Preferred Qualifications:

• Tape-out experience with high-performance ASICs or SoCs
• Familiarity with HLS tools, formal verification, or low-power design flows
• Experience with FPGA prototyping platforms (Xilinx, Intel/Altera)
• Background in memory controller or storage-class memory architecture
• Prior experience in CXL controller design or verification

Why Join Netlist:

• Contribute to pioneering work in CXL, DDR5, and next-gen memory technologies
• Work alongside some of the industry's top engineers in ASIC, memory systems, and storage
• Enjoy a collaborative and agile work culture focused on innovation
• Competitive compensation and comprehensive benefits package
• Flexible work environment including remote opportunities