Advanced Packaging Design Engineer PCB / Substrate / 2.5D3D - Bay Area, CA

Overview

Hybrid
Depends on Experience
Accepts corp to corp applications
Contract - Independent
Contract - W2
Contract - 12 Month(s)

Skills

PCB
HPC
Packaging Design Engineer
Cadence APD
Virtuoso
DDR
EMIB
CPO
CPC
Python
Optical routing

Job Details

Advanced Packaging Design Engineer PCB / Substrate / 2.5D 3D

Location: Bay Area, CA (Hybrid) | Type: Contract
Domain: Semiconductor | AI | High-Performance Computing (HPC)

A leading semiconductor and AI-HPC solutions company seeks an experienced Advanced Packaging Design Engineer to drive next-gen package design and technology development for high-performance computing, AI, and networking products.

Responsibilities:
Lead package/substrate design feasibility for new PCB and interposer technologies.
Develop libraries, design workflows, and automation methods.
Collaborate with silicon, IP, SI/PI, thermal/mechanical, test, and production teams.
Define advanced design rules, materials, and interposer/substrate roadmaps.
Create package outline drawings, bonding diagrams, and 3D models.

Requirements:
BS (15+ yrs), MS (12+ yrs), or PhD (8+ yrs) in EE/ME or related field.
Proven experience in advanced PCB/substrate design for manufacturability and reliability.
Hands-on skills: Cadence APD & SiP, AutoCAD, SolidWorks, Virtuoso.
Expertise in DDR, SerDes, PCIe, Ethernet, D2D/D2H layout.
Strong signal/power integrity knowledge; familiarity with 2.5D/3D, CoWoS, EMIB, CPO/CPC.
Understanding of chip-package interactions, failure mechanisms, and thermal materials.

Preferred: Optical routing, Python scripting, supplier influence, and global collaboration skills.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.