FPGA/ASIC Verification Engineer

Overview

BASED ON EXPERIENCE
Contract - W2
Contract - Independent
Contract - 6+ mo(s)

Skills

Design Of Experiments
Interfaces
FPGA
ASIC
Test Plans
Dimensional Modeling
Quality Assurance
Testing
Computer Engineering
Test Cases
SDF
Durable Skills
Electrical Engineering
Computer Science
UVM
SystemVerilog
Python
Operating Systems
Linux
Android
Formal Verification
Ethernet
SPI
AXI
JTAG
SANS
Modeling
Health Care
Legal
Insurance

Job Details

Job Title: FPGA/ASIC Verification Engineer
Duration : 6 months with possible extension
Pay range : $85-100/hr. on W2 (DOE)
Location - Hybrid, Goleta, CA

Client - Fortune 25 company.
Work Schedule: Normal PST business hours, Monday - Friday

Project Overview:

  • The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to driven the internal components and send data.

Overall Responsibilities:
  • As a FPGA/ASIC Design Verification Engineer, you will own functional verification for a custom controller. You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.
  • In this role, you will develop test plans for functional units and subsystems. You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance. In the final stages, you will also run GLS related simulations.
Top 3 Daily Responsibilities:
  • Responsibilities include the following:
  • UVM/python test development for driving VIPs and other stimulus drivers
  • Generation of test components such as monitors, scoreboards and python models
  • Coverage closure and GLS bringup and testing
Mandatory Skills/Qualifications: (All skills, both technical and soft, required to be successful in the role)
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 6+ years of experience with verification methodologies and languages such as UVM and SystemVerilog.
  • Experience developing and maintaining verification testbenches, test cases, and test environments.
  • Experience in all aspects of verification life cycle, specifically, SDF and GLS simulations
  • Experience in ethernet and SPI required

Non-Essential Skills/Qualifications: (Skills that would be nice to have but are not essential in the role)
  • Master s degree in electrical engineering, Computer Science, or related field.
  • UVM/System Verilog experience 5+ years
  • High proficiency in python
  • Knowledge of general-purpose operating systems such as Linux and Android.
  • Experience in assertions and formal verification preferred
  • Experience in ethernet, SPI, AXI, JTAG preferred
  • Experience in analog and real number modeling preferred


Pride Global offers eligible employee's comprehensive healthcare coverage (medical, dental, and vision plans), supplemental coverage (accident insurance, critical illness insurance and hospital indemnity), 401(k)-retirement savings, life & disability insurance, an employee assistance program, legal support, auto, home insurance, pet insurance and employee discounts with preferred vendors.

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