Principal Engineer, Physical Design

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

This role is based in Santa Clara, CA. You will be required to relocate if you work with this team. You will work with both local and global team members on the physical design of complex chips and lead the development of advanced methodologies that enable scalable, high-performance implementation. As a Principal Engineer, you will operate at the intersection of technical depth and strategic influence, driving innovation across teams and projects.

As a Principal Engineer in the Physical Design team, you will:

• Architect and lead the development of next-generation physical design methodologies and automation flows
• Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure
• Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges
• Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution.
• Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization
• Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors
• Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
• Strong understanding of standard RTL to GDS flows and methodology
• Strong scripting skills in languages such as Perl, tcl, and Python
• Strong object-oriented programming skills
• In-depth understanding of digital logic and computer architecture
• In-depth knowledge of Verilog/VHDL
• Good communication skills and self-discipline contributing in a team environment

Expected Base Pay Range (USD)
146,850 - 220,000, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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