Principal SoC Memory Subsystem Architect

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Principal SoC Memory Subsystem Architect, you will drive the definition of SoC memory and cache subsystems for next-generation mobile and automotive products.

This is a senior technical lead role, you will identify and analyze emerging use cases, as well as, proposing new and innovative SoC memory architectures to efficiently support them. Your solid background in architecture foundation, detailed knowledge of cache hierarchy, memory subsystem, and SoC architecture are desired for success. You are empowered to experiment with new ideas while contributing to impactful ongoing deliverables and broadening your knowledge of whole SoC design.

Key Responsibilities Include:

• You are passionate about identifying, proposing, and delivering new SoC architecture and architecture features for products in new and existing markets - particularly around smartphone and mobile platforms.
• You enjoy performing high-level performance modeling and analysis of hardware features, applications, benchmarks, and complex uses cases.
• You are a domain expert in one or more technical areas. You understand and can analyze the impact of system-level architectural trade-offs (including CPU, GPU, NPU, ISP, memory subsystems, and system software).
• You are highly analytical and can leverage a data-driven approach to drive consensus around complex architectural proposals.
• You are skilled at creating necessary simulation/analysis tools to evaluate complex memory subsystem use cases such as gaming and camera use cases.
• You excel at delivering architecture proposals and specifications to the design team.
• You thrive on driving cross-company collaboration by communicating and articulating architecture proposals clearly and effectively, across audiences ranging from hardware software engineers to architecture community peers, and to technology leadership.

Skills and Qualifications

• 15+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 13+ years of experience with a Master's Degree, or 11+ years of experience with a PhD
• Extensive experience in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation, especially around CPU - memory subsystems
• High proficiency in leveraging existing simulation capabilities or create new simulation capabilities where necessary
• Detailed knowledge of cache subsystems including caching policies and understanding the tradeoffs of latency, bandwidth and hierarchies
• Detailed knowledge of memory subsystem design to include existing/emerging JEDEC memory standards
• Knowledge of in Interconnect and bus protocols - CHI/ACE interconnect experience preferred
• Strong written and verbal communication skills
• Knowledge of high performance, high efficiency design
• Experience with the Android Ecosystem and analysis tools is a plus
• Experience with Arm Architecture and ecosystem is a plus

Our Team

We're building a new team to influence the product roadmap for a market-leading system IP solution. Our team focuses on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team's culture.

Pay Transparency

At Samsung - SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $216,521 and $359,527. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Trade Secrets

By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.

#SARC #ACL

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