RTL Design Engineer

Title: RTL Engineer

Location: San Jose, CA | San Diego, CA | Austin Texas

Duration: 6+ months (Possible Extension-Long Term Project)

 Job Description

• As a senior RTL design engineer, you will work as part of a memory controller IP design team.
• You will be tasked with driving the RTL design, performance and power optimization of various sub-blocks of the dynamic memory controller.
• Solid engineer foundation and RTL design experience is desired for success.

Key responsibilities include:

• Produce quality RTL on schedule meeting PPA goals
• Responsible for key blocks within the Memory Controller
• Engage with others for PPA optimization
• Partner with the physical design and CAD team to resolve implementation level details
• Work closely with design verification to test plan and otherwise ensure proper functionality
• Deliver quality micro-architectural level documentation

Minimum requirements:

• BSEE, Computer Engineer or comparable and  7+ years of experience
• Experience owning and driving the RTL design of various sub-blocks of the memory controller for the high performance digital designs
• Demonstrated experience of successful Architectural through RTL design experience on high performance and high efficiency digital designs
• Detailed knowledge of memory subsystem design
• Detailed knowledge of existing and emerging JEDEC memory standards

Preferred candidate will possess the following:

• Energetic, curiosity, and passion in logic design
• Knowledge of interconnect and bus protocols with AMBA interconnect experience preferred
• Knowledge of cache subsystem design and optimization