Overview
On Site
$65 - $70
Accepts corp to corp applications
Contract - W2
Contract - Independent
Contract - 6 Month(s)
Skills
PCIe
RTL
ASIC
Verilog
SerDes
Job Details
Position: RTL Design engineer with strong experince on PCIe Location: San Jose, CA / Irvine, CA / Austin, TX Onsite
Duration: 06 Months
Candidate Roles and Responsibilities
PCIe System Expertise:
Deep understanding and hands-on experience in PCIe system architecture, with an emphasis on physical layer design and specification.
Ensure compliance with PCIe specifications, including but not limited to PIPE interface, LTSSM, 8b/10b and 128b/130b encoding, EIEOS intervals, equalization and electrical idle conditions.
Deep understanding of PCIe retimer specification.
Lead silicon bring-up activities, troubleshoot, and debug PCIe related issues.
ASIC Design and Development:
Design, implement, and verify ASIC components with a focus on PCIe physical layer requirements.
Utilize Verilog and SystemVerilog for development, ensuring compliance with performance and design standards.
SerDes Technology:
Extensive knowledge of SerDes technology, including understanding its operation, design challenges, and integration into high-speed communication interfaces.
Collaboration and Leadership:
Work closely with cross-functional teams to drive the design process from concept to implementation.
Provide guidance and expertise in PCIe-related discussions and decisions.
Quality Assurance and Validation:
Ensure the highest quality of design through rigorous testing, validation, and adherence to industry standards.
Deep understanding and hands-on experience in PCIe system architecture, with an emphasis on physical layer design and specification.
Ensure compliance with PCIe specifications, including but not limited to PIPE interface, LTSSM, 8b/10b and 128b/130b encoding, EIEOS intervals, equalization and electrical idle conditions.
Deep understanding of PCIe retimer specification.
Lead silicon bring-up activities, troubleshoot, and debug PCIe related issues.
ASIC Design and Development:
Design, implement, and verify ASIC components with a focus on PCIe physical layer requirements.
Utilize Verilog and SystemVerilog for development, ensuring compliance with performance and design standards.
SerDes Technology:
Extensive knowledge of SerDes technology, including understanding its operation, design challenges, and integration into high-speed communication interfaces.
Collaboration and Leadership:
Work closely with cross-functional teams to drive the design process from concept to implementation.
Provide guidance and expertise in PCIe-related discussions and decisions.
Quality Assurance and Validation:
Ensure the highest quality of design through rigorous testing, validation, and adherence to industry standards.
Document designs, analyses, and test results comprehensively.