Senior ASIC / FPGA Design Verification Engineer with UVM

Overview

On Site
$80 - $120
Contract - Independent
Contract - W2
Contract - 12 Month(s)

Skills

ASIC
FPGA
Design Verification
UVM
Verilog
SystemVerilog
VHDL
UVC

Job Details

Title: ASIC/FPGA Design Verification Engineer -

Onsite in Los Angles, CA (6-12 Month Contract)

Job Description: Develop UVM simulation plan based on design specs. Customize or create UVC, Scoreboard, Monitor, and test cases. Ensure functional and code coverage meets project thresholds. Document results.

Expectations for Contractors:

  • Ideally, capable of handling complex blocks independently.
  • Responsible for interface or functional block verification.
  • Develop test plans adhering to provided templates and block requirements.
  • Develop UVCs, scoreboards, and other testbench components.
  • Execute and troubleshoot test cases, report DUT failures.
  • Assess and report coverage.
  • Weekly status updates and proactive communication.
  • Equivalent communication and productivity as full-time employees.

Education/Experience: Bachelor's degree in engineering, computer science, mathematics, physics, or chemistry with 7+ years of related experience, or equivalent combination of education and experience. ABET accreditation preferred but not required.