Overview
On Site
$60 - $65
Contract - W2
Contract - Independent
Skills
Design Verification
UVM
Test Planning
Debugging
Silicon
Computer Architecture
C++
Job Details
Job Title: Senior Engineer
Location: San Jose, CA (5 days to offce weekly)
Contract: 6+ Months
Job Description
Design Verification expertise in System Verilog /UVM Unit/Module level Verification
Experience in test planning and debugging complex designs
Full silicon design lifecycle experience
Strong background in developing UVM Testbenches from scratch
Deep understanding of Computer Architecture
Test Planning, Coverage, Bring up Phase, Design Freeze and ECO Phase
Experience with caches and memory subsystems (preferred, but not mandatory)
C++ Nice to have
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