SystemC/TLM2 Performance Modeling at San Jose CA

  • San Jose, CA
  • Posted 49 days ago | Updated 15 days ago

Overview

On Site
Depends on Experience
Full Time

Skills

SystemC
Performance modeling
UVM

Job Details

Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.

Collaborate with cross teams to integrate models into Client tools used for system-level designs, ensuring proper functionality and performance.

Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.

Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.

Create clear and comprehensive documentation for models, including usage guidelines and design specifications.

Cycle approximate performance models

SV/UVM Functional and Performance Verification

PCIe/AXI knowledge

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