Overview
On Site
Depends on Experience
Full Time
Skills
Design Verification expertise in System Verilog /UVM for Unit/Module level VerificationShould have Lead Design Verification Team ( Min 5 Members)Strong background in developing UVM Testbenches from scratchExperience in VIP Integration and Bring upPorting Existing Verilog/VHDL environment to UVM based EnvironmentExperience in test planning
Coverage Coding and DebuggingDeep Knowledge of AMBA Protocol is must
Job Details
Role- Tech Lead FPGA
Location: Seattle, Washington
Job Type- Fulltime
Onsite: YES customer location
Salary- $155K + Benefits
Note- Please share the resume to Email:
JD:
He should have some lead experience, even hands on experience in also fine.
- Looking 12 to 18 years as a Lead
- Design Verification expertise in System Verilog /UVM for Unit/Module level Verification
- Should have Lead Design Verification Team ( Min 5 Members)
- Strong background in developing UVM Testbenches from scratch
- Experience in VIP Integration and Bring up
- Porting Existing Verilog/VHDL environment to UVM based Environment
- Experience in test planning ,Coverage Coding and Debugging
- Deep Knowledge of AMBA Protocol is must
Regards
Rahul Srivastava
IT Technical Recruiter
Diverse Lynx LLC.
Office: ext : 341/ Whatsapp Number only:
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.