Verification Engineer - Onsite

  • Longmont, CO
  • Posted 50 days ago | Updated 14 days ago

Overview

On Site
$66.43 - $71.43
Contract - W2
Contract - 7 Month(s)

Skills

RTL verification
Verilog
System Verilog
Modelsim
VCS
UVM
PCIe device testing DMA
CXL
IDE
VIP models
traffic generators
checkers
UVM verification methodologies
UVM verification environments
verification methodologies
verification infrastructure
PCIe
serial protocols
simulation tools
test environments
FPGA
VIP
IP development
IP verification
hardware modeling
develop
debug
analytical
communication

Job Details

Title: Verification Engineer - Onsite


Mandatory skills:


RTL verification, Verilog, System Verilog, Modelsim, VCS, UVM,
PCIe device testing DMA, CXL, IDE, VIP models, traffic generators, checkers,
UVM verification methodologies, UVM verification environments,
verification methodologies, verification infrastructure,
PCIe, serial protocols, simulation tools, test environments,
FPGA, ModelSim, VCS, VIP,
IP development, IP verification, hardware modeling,
develop, debug, analytical, communication


Description:


JOB DUTIES:
Participate in design and functional verification of a block(s) of IP. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block and overall system. Be responsible for developing and improving simulation test environments consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally and work within the existing verification infrastructure. Be familiar with hardware modeling and/or assertion-based verification methods.

In this role you will be part of a PCIe development and productization team. A majority of the verification will target PCIe device testing DMA, CXL, IDE, VIP models, traffic generators/checkers, etc.

EXPERIENCE:
8 or more years of proven verification experience on Verilog and System Verilog for IP development and verification required
Familiar with UVM verification methodologies and environments
Strong debug skills
Experience with simulation tools ModelSim/VCS and VIPs
Experience in Verilog/SystemVerilog
Strong analytical skills and attention to detail
Excellent written and communication skills
Familiarity with PCIe and serial protocols is a bonus
Client FPGA and tools experience is a bonus

Essential skills:
RTL verification experience, Verilog/System Verilog, Modelsim/VCS, UVM

Nice-to-have skills:
FPGA Experience (Client FPGA preferred), Client software experience


VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.


Contact Details :

VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008

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About VIVA USA INC