Chip Verification Engineer Jobs in 60532

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Hardware Engineering and R&D Silicon Verification Engineer

IDC Technologies

Remote

Contract, Third Party

Dear Applicant, Hope you are doing well We have an urgent requirement of Hardware Engineering and R&D with one of our global consulting client. Kindly click to apply if you are available and interested in the job role mentioned below. Title: Hardware Engineering and R&D - Silicon Verification Engineer Location: 100% Remote Job Type: Long Term Contract Job Description: Skills Required: Years of Experience Required: 3 overall years of experience in the field. The ideal candidate would contain

Senior Technical Engineer - Identity Access Management - Tethering & Verification Identity Platform

CSM Technologies Inc

Remote

Third Party, Contract

Title: Senior Technical Engineer - Identity Access Management - Tethering & Verification Identity Platform Location: San Jose, CA, Austin, TX (Remote ok) Duration: Long Term Contract Job Description: Qualifications: Bachelor's Degree in Computer Science or related field.A solid grounding in Computer Science fundamentals.15+ years of experience building successful production software systems.5+ years of relevant experience in Digital Identity & Access Management domain & solid understanding of Id

FPGA Verification Engineer

Innova Solutions, Inc

Remote

Contract

Innova Solutions is immediately hiring for FPGA Verification Engineer Position type: Full Time, Contract 100% Remote Duration: 12 months As an FPGA Verification Engineer you will: Verify FPGA firmware for a military applicationReview requirements for a new firmware designs using enterprise tools such as Jama ConnectCreate a test approach, outline, and description for chip and module level verification in Microsoft WordImplement simulation testbenches to verify requirements in QuestaSim using

Senior ASIC / FPGA Design Verification Engineer

Technical Link

Remote

Contract

6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing

ASIC Verification Engineer

Q1 Technologies, Inc.

Remote or Santa Clarita, California, USA

Full-time, Contract, Third Party

Job Title : ASIC Verification Engineer Location: Bay Area, CA & Austin, Texas (Onsite only) Opening 10 Mandatory Skills: Design Verification, UVM, IP, SOC, System Verilog Job Description: Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units