FC Jobs in San Jose, CA

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SDC Engineer

PeopleNTech

San Jose, California, USA

Contract

SDC Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/TempusWhat You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop efficient methodology to promote

STA Engineer (Static Timing Analysis )

PeopleNTech

San Jose, California, USA

Contract

Position: STA Engineer (eInfochips Inc) Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop effi

Hardware Engineer

Experis

San Jose, California, USA

Full-time

We have a job opportunity open with our client. I was wondering if you are available in job market for new roles. Let me know your view on below role and share your resume ,if interested. Hardware Engineer Mid. Onsite from day 1 San Jose ,CA Contract (12+ months) What candidate will Be Doing: Technical: Being a member of design team who oversees fullchip STA/ SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL

STA Engineer (eInfochips Inc)

Arrow Electronics, Inc.

San Jose, California, USA

Full-time

Position: STA Engineer (eInfochips Inc) Job Description: Position: STA Engineer (eInfochips Inc) Location: San Jose CA (Day-1 Onsite) What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC chang

SDC Engineer (eInfochips Inc)

Arrow Electronics, Inc.

San Jose, California, USA

Full-time

Position: SDC Engineer (eInfochips Inc) Job Description: Position: SDC Engineer (eInfochips Inc) Location: San Jose CA (Day-1 Onsite) What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC chang

ASIC Engineering Technical Leader - SDC

Cisco Systems, Inc.

San Jose, California, USA

Full-time

The application window is expected to close on: June 27, 2025. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role requires being onsite in San Jose, CA 4+ days/week. Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-

Staff Software Engineer - Storage Systems and Protocols

Samsung Electronics America

San Jose, California, USA

Full-time

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of

Senior CPU Implementation Methodology Engineer

NVIDIA Corporation

Santa Clara, California, USA

Full-time

We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computi

Senior Storage Engineer

SS&C Technologies Inc

Utah, USA

Full-time

As a leading financial services and healthcare technology company based on revenue, SS&C is headquartered in Windsor, Connecticut, and has 27,000+ employees in 35 countries. Some 20,000 financial services and healthcare organizations, from the world's largest companies to small and mid-market firms, rely on SS&C for expertise, scale, and technology. Job Description Title: Sr. Storage Engineer Locations: REMOTE / Kansas City, MO Note: While this is a remote position, there may be occasional

Static Timing Analysis? Engineer

Apolis

San Jose, California, USA

Full-time, Contract

Job Title: Static Timing Analysis Engineer Location: San Jose ,CA (Onsite) Contract: 12+ MonthsWhat candidate will Be Doing: Technical Requirement: Being a member of design team who oversees fullchip STA/ SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes ba

STA Engineer

Mirafra Inc

San Jose, California, USA

Full-time

Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery. Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates Synthesis Tools: Synopsys DC/DCG/FC. Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cade

STA Engineer

Kutir Inc

San Jose, California, USA

Contract, Third Party

Position: STA Engineer Location: Onsite San Jose CA Duration: 6+ months In Person Interview is must Job Description: Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or t

STA Engineer

Cybotic Systems LLC

San Jose, California, USA

Contract

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop efficient methodolog

SDC Engineer

PeopleNTech

San Jose, California, USA

Third Party, Contract

Must have/Primary skills: Full chip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees full chip SDCs and works with physical design and DFT teams to close full chip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develops efficient methodology to promote block level SDCs to full chip, and to bring f