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Senior Design Verification Engineer

Microsoft Corporation

US

Full-time

The Artificial Intelligence Silicon Engineering team is responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner. We are seeking a Senior Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate should be a highly motivated self-starter who will thrive in this cutting-edge technical environment. You will be part of the design verificat

Design Verification Engineer

Innova Solutions, Inc

San Francisco, California, USA

Full-time

Innova Solutions is immediately hiring a Design Verification Engineer Position type: Full Time. Duration: Full Time Location: San Francisco, CA (Onsite) As a Design Verification Engineer, you will: Minimum Qualifications: 7+ years of ASIC verification experience with UVM (or similar methodology/tools) and excellent Verilog/System Verilog programming skillsMust have previously worked on an engineering team that has taped out & successfully shipped at least one high speed processor or ASIC before.

Design Verification Engineer

National Computer Systems

Campbell, California, USA

Contract

Role: Design Verification Engineer Work Location: Santa Clara, CA Contract to Hire role Preferred Qualifications: 7+ years of experience in pre-silicon design verification Proficiency in C-shell scripting, Verilog-HDL & System Verilog. Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. SOC Verification experience using ARM Cortex Microcontroller is required. Experience with advanced peripheral bus Verification IP s such as GPIO, UART, SPI, SW, JTAG, and I2C. Proficient with

UVM/ SystemVerilog Design Verification Engineer

U.S. Tech Solutions Inc.

Goleta, California, USA

Contract

Job Description: As a Verification Engineer, you will own functional verification for a custom controller. You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.In this role, you will develop test plans for functional units and subsystems. You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance. In the final stages, you will also run

Principal Design Verification Engineer

Microsoft Corporation

Mountain View, California, USA

Full-time

The Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner. We are looking for a Principal Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon

Principal Design Verification Engineer

Microsoft Corporation

Mountain View, California, USA

Full-time

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Principal Design Verification Engineer to work on leading edge IP (intellectual property) development as part of the Semi-custom and Central

Design Verification Engineer - Senior - Onsite

VIVA USA INC

Folsom, California, USA

Contract

Title: Design Verification Engineer - Senior - Onsite Mandatory skills: Design Verification C/C++, SV, UVM scripting, Perl, Ruby, Makefile, System Verilog AXI protocol, Bootcode Verification UVM verification, testbench components, test libraries, IPs, Control Fabric, IP level testing processor architecture, digital design, technical support, technical innovation Description: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key cont

ASIC Engineer, Design Verification

Meta Platforms, Inc. (f/k/a Facebook, Inc.)

Sunnyvale, California, USA

Full-time

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following position in Sunnyvale, CA: ASIC Engineer, Design Verification: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. (ref. code REQ-2405-137726: $208,936/year - $234,520/year). Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus or eq

Design Verification Engineer job opportunity at Folsom, CA

Infobahn Softworld Inc.

Santa Clara, California, USA

Contract

Role Title: Design Verification Engineer Location: Folsom, CA Duration: 12+ months contract THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve Client's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well a

FPGA Design Verification Engineer

GENERAL DYNAMICS MISSION SYSTEMS

Dedham, Massachusetts, USA

Full-time

Basic Qualifications Requires a Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience. CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified

Design Verification Engineer

Mirafra Inc

San Jose, California, USA

Full-time

Role: Design Verification Engineer Location: San Jose CA Job Description: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA p

Design Verification engineer

Viva Tech Solutions

Folsom, California, USA

Full-time

Title: Design Verification engineer Type: FTE Location: Folsom CA Onsite- Day 1 onwards Key Responsibilities: Domain: VLSI /Semiconductor Mandate skill- Verification OVM UVMUtilize hands-on experience in SystemVerilog, UVM, and Testbench development to facilitate the verification process.Perform thorough debugging and troubleshooting to identify and resolve issues efficiently.Conduct full-chip and SoC simulations to validate design functionality and performance.Demonstrate expertise in subsyst

Senior Design Verification Engineer

Microsoft Corporation

Mountain View, California, USA

Full-time

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting-edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Senior Design Verification Engineer to work on leading-edge Intellectual Property (IP) development as part of the Semi-Custom and Central Int

Design Verification Engineer

West Coast Consulting LLC

SARC GPU

Contract

Job Description Vertical Technical As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities: Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug tools. Maintain efficient and clean regression status Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification. Review Architecture and Micro-

Design Verification Engineer (eInfochips Inc.)

Arrow Electronics, Inc.

Massachusetts, USA

Full-time

Position: Design Verification Engineer (eInfochips Inc.) Job Description: What You'll Be Doing: Understanding of Ethernet / project specifications.Writing Test plan and coverage plan.Write testcases/scenarios.Update existing testbench components like generators, drivers, and monitors.Debug existing tests failing in the regression.Work on Subsystem and system level verification. What We Are Looking For: At least 10+ years of experience in System Verilog HVL and C++/C.At least 10+ years of exper

Design Verification Engineer

LTIMindtree

Mountain View, California, USA

Full-time

About Us LTIMindtree is a global technology consulting and digital solutions company that enables enterprises across industries to reimagine business models, accelerate innovation, and maximize growth by harnessing digital technologies. As a digital transformation partner to more than 700+ clients, LTIMindtree brings extensive domain and technology expertise to help drive superior competitive differentiation, customer experiences, and business outcomes in a converging world. Powered by nearly 90

Design Verification Engineer

Apple, Inc.

Sunnyvale, California, USA

Full-time

Summary Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible? As part of our team, you will be responsible for and contribute to verifying high-throughput, complex cellular baseband modems and transceiver link controllers: You will be crafting highly reusable premier UVM test benches, implementing coverage driven and directed test cases working with cross functional teams, deploying new tools and methodologies to improve quali

Design Verification Engineer

Apple, Inc.

San Diego, California, USA

Full-time

Summary Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible? As part of our team, you will be responsible for and contribute to verifying high-throughput, complex cellular baseband modems and transceiver link controllers: You will be crafting highly reusable premier UVM test benches, implementing coverage driven and directed test cases working with cross functional teams, deploying new tools and methodologies to improve quali

Design Verification Engineer

Apple, Inc.

Austin, Texas, USA

Full-time

Summary Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Description APPLE INC has the following available in West Lake Hills, Texas. Create software to verify architecture and functionality of pre-sil

Design Verification Engineer (eInfochips Inc.)

Arrow Electronics, Inc.

Massachusetts, USA

Full-time

Position: Design Verification Engineer (eInfochips Inc.) Job Description: What You'll Be Doing: Understanding of Ethernet / project specifications.Writing Test plan and coverage plan.Write testcases/scenarios.Update existing testbench components like generators, drivers, and monitors.Debug existing tests failing in the regression.Work on Subsystem and system level verification. What We Are Looking For: At least 10+ years of experience in System Verilog HVL and C++/C.At least 10+ years of expe