vcs Jobs in san jose, ca

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RTL Engineer

Cloudious

Santa Clara, California, USA

Third Party, Contract

In-Person Interview Role: Integrate RISC-V Core to SoC Key Responsibilities Integrate RISC-V CPU cores into SoC designs, collaborating with cross-functional teams (DV, physical design, architecture, verification, and post-silicon validation) to ensure seamless delivery. Develop and optimize RTL (using Verilog/SystemVerilog) for core, interconnect, and memory subsystems. Evaluate and integrate third-party IP, ensuring performance, power, and area (PPA) targets are met. Debug complex RTL/logic i

RTL Engineer: Integrate RISC-V Core to SoC

Intelliswift Software Inc

Santa Clara, California, USA

Contract

Job Title: RTL Engineer: Integrate RISC-V Core to SoC Location(s): Santa Clara, CA - Onsite Must Have skills: 5+ years of experience in RTL design, SoC integration, or related areas.Strong hands-on experience with hardware description languages (Verilog, SystemVerilog, VHDL), EDA tools, and simulators (VCS, NC, Verilator).Deep understanding of SoC design, integration, and high-performance interfaces (e.g., AXI, TileLink, PCIe, Ethernet).Proven ability to debug and optimize designs for functiona

Silicon DD Engineer III

BCforward

Palo Alto, California, USA

Contract

Silicon DD Engineer BCforward is currently seeking a highly motivated Silicon DD Engineer Role for a Remote Role! Position Title: Silicon DD Engineer Location: Remote Anticipated Start Date: 8/11/25 Please note this is the target date and is subject to change. BCforward will send official notice ahead of a confirmed start date. Expected Duration: 12+ Months Job Type: Contract - [FULL TIME (40 Hours a week)] Pay Range: $78.72/hr-$82.58/hr Please note that actual compensation may vary wi

RTL Engineer

Cloudious

Santa Clara, California, USA

Contract

Title: RTL Engineer Location: Santa Clara, CA (Day-1 onsite) Duration: 6 Months Role: Integrate RISC-V Core to SoC Key Responsibilities Integrate RISC-V CPU cores into SoC designs, collaborating with cross-functional teams (DV, physical design, architecture, verification, and post-silicon validation) to ensure seamless delivery. Develop and optimize RTL (using Verilog/SystemVerilog) for core, interconnect, and memory subsystems. Evaluate and integrate third-party IP, ensuring performance, power,

Sr SoC Gate-Level Simulation (GLS) Engineer

Yoh - A Day & Zimmerman Company

Remote or Santa Clara, California, USA

Full-time

Sr SoC Gate-Level Simulation (GLS) Engineer In need of a solid Gate-Level Simulation Engineer to support complex System-on-Chip (SoC) development. In this contract role, you ll be responsible for verifying gate-level functionality, timing, and power across SoC subsystems. You'll work closely with RTL, physical design, and verification teams to ensure accurate coverage and system-level stability. Scope: Develop and apply GLS methodologies for high-performance SoC projects Run gate-level simulati

Sr SoC Gate-Level Simulation (GLS) Engineer

Yoh - A Day & Zimmerman Company

Remote or Santa Clara, California, USA

Full-time

Sr SoC Gate-Level Simulation (GLS) Engineer In need of a solid Gate-Level Simulation Engineer to support complex System-on-Chip (SoC) development. In this contract role, you ll be responsible for verifying gate-level functionality, timing, and power across SoC subsystems. You'll work closely with RTL, physical design, and verification teams to ensure accurate coverage and system-level stability. Scope: Develop and apply GLS methodologies for high-performance SoC projects Run gate-level simulati