verification engineer Jobs in san francisco%2c ca

Refine Results
1 - 7 of 7 Jobs

Software Verification Engineer (Non-Clinical)

Cynet Systems

•

Palo Alto, California, USA

Contract, Third Party

We are looking for Software Verification Engineer (Non-Clinical) for our client in Palo Alto, CA Job Title: Software Verification Engineer (Non-Clinical) Job Location: Palo Alto, CA Job Type: Contract Job Description: Pay Range $50hr - $55hr Responsibilities: Test Planning and Design.Develop comprehensive test plans, test cases, and test scripts based on software requirements and design specifications.Ensure test plans cover all functional and non-functional requirements, including performance,
Easy Apply
Posted 18 hours ago | Updated 2 hours ago

Software Verification Engineer (Clinical)

Cynet Systems

•

Palo Alto, California, USA

Third Party, Contract

We are looking for Software Verification Engineer (Clinical) for our client in Palo Alto, CA Job Title: Software Verification Engineer (Clinical) Job Location: Palo Alto, CA Job Type: Contract Job Description: Pay Range $50hr - $55hr Responsibilities: Test Planning and Design.Develop comprehensive test plans, test cases, and test scripts based on software requirements and design specifications.Ensure test plans cover all functional and non-functional requirements, including performance, reliabil
Easy Apply
Posted 19 hours ago | Updated 2 hours ago

Verification Engineer

Happiest Minds Technologies Limited

•

Fremont, California, USA

Contract, Third Party

Verification Engineer Fremont, CA BSEE or BSCS, or equivalent 5+ years of ASIC/FPGA verification experience using SystemVerilog / UVMMust have experience with:Verification flow using Questa simulationDeveloping verification plansDesigning and implementing SystemVerilog / UVM test benches for constrained-random verificationDeveloping functional coverage modelsWriting and debugging directed and random test casesExperience with automation/scripting (Python, Perl, sed, awk, tcl/tk, sh)Experience wit
Easy Apply
Posted 31 days ago

SW Design engineer for Software integration and Verification Testing

Violet Ink

•

Alameda, California, USA

Contract

We need engineers who have experience in design & development and testing. But this job does not include any design/development. Understand the design developed in C language for micro-controller based on Non-RTOS and RTOS environment for a highly safety critical handheld medical device. Understand the GUI design developed in C++ language for micro-controller based RTOS environment for a highly safety critical handheld medical device. Perform Requirement analysis and identify gaps. Identify t
Easy Apply
Posted 21 days ago

Senior ASIC / FPGA Design Verification Engineer

Technical Link

•

Remote

Contract

6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing
Easy Apply
Posted 60+ days ago | Updated 1 day ago

ASIC Verification Engineer

Q1 Technologies, Inc.

•

Remote or Santa Clarita, California, USA

Full-time, Contract, Third Party

Job Title : ASIC Verification Engineer Location: Bay Area, CA & Austin, Texas (Onsite only) Opening 10 Mandatory Skills: Design Verification, UVM, IP, SOC, System Verilog Job Description: Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units