UVM Jobs in Austin, TX

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Emulation Methodology Engineer @ Austin, TX - (Onsite)

Infobahn Softworld Inc.

Austin, Texas, USA

Third Party, Contract

We have an immediate opportunity with one of our direct clients. Please find the job description below and if you are interested, please forward your resume and share below details: Best contact number: Work Authorization: Hourly Payrate expected (W2): Month & Day of birth (MM/DD): Present Location & Zip-code: LinkedIn: Role Title: Emulation Methodology Engineer Location: Austin, TX 100% onsite in Austin, TX. Open for Hybrid after getting established in the role. Duration: 6+ months con

Design Verification Engineer

Apple, Inc.

Austin, Texas, USA

Full-time

Summary Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Description APPLE INC has the following available in West Lake Hills, Texas. Create software to verify architecture and functionality of pre-sil

GPU Design Verification Lead

Qualcomm Technologies

Austin, Texas, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: GENERAL SUMMARY: Architects, designs, implements, verifies, and optimizes performance and power of GPU cores. Responsible for verification of Graphics IP , and performing pre- and post-silicon verification to verify correctness and ensure performance and power goals are met. The responsibilities of this role include: Owning and executing on key independent tasks towards

Security Architect

TechMiners LLC

Remote

Contract

- Strong debugging, Analytical and problem-solving skills- Experience with UVM and ARM Bus protocols. Expertise on UVM based verification Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved

Senior ASIC / FPGA Design Verification Engineer

Technical Link

Remote

Contract

6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing

DV Engineer

Mastech Digital

Austin, Texas, USA

Contract

Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a DV Engineer for our client in the Engineering domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract position, and the client is looking for someone to start immediately. Duration: 6+ Months Contract with possible extension Location: Austin, TX/San Jose Role: Design Ve

Emulation Methodology Engineer

Netwoven

Austin, Texas, USA

Contract

Job Description: Develop and drive improvements using the latest emulation technology from industry. Support emulation methodology & emulations tools (Veloce, Palladium & ZeBu) as part of central methodology team. Creating App Notes & Articles for Frequently Asked questions Develop emulation tools, workflows and infrastructure in collaboration with RTL, verification, validation and SW teams for productivity during debug, runtime, and data analysis of results from emulation runs. Develop emulatio

ASIC Verification Engineer

Yoh - A Day & Zimmerman Company

Remote or Austin, Texas, USA

Full-time

ASIC Verification Engineer Reviewing the product designs and noting likely points of failure. Designing verification methodology based on product designs and failure points. Determining testing environments and verification tools. Planning the method of sequence for testing operations. Instituting and tweaking testing mechanisms and protocols. Writing up final test procedures and training QC staff. Qualificatios Bachelor s or Master s in Electrical or Computer Science 4 years of Design Verificat

ASIC Verification Engineer

Q1 Technologies, Inc.

Remote or Santa Clarita, California, USA

Full-time, Contract, Third Party

Job Title : ASIC Verification Engineer Location: Bay Area, CA & Austin, Texas (Onsite only) Opening 10 Mandatory Skills: Design Verification, UVM, IP, SOC, System Verilog Job Description: Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units