UVM Jobs in San Francisco, CA

1 - 8 of 8 Jobs

Design Verification EngineerJob Title - Design Verification Engineer

Innova Solutions, IncCompany Name - Innova Solutions, Inc

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San Francisco, California, USA

Full-time

Innova Solutions is immediately hiring a Design Verification Engineer Position type: Full Time. Duration: Full Time Location: San Francisco, CA (Onsite) As a Design Verification Engineer, you will: Minimum Qualifications: 7+ years of ASIC verification experience with UVM (or similar methodology/tools) and excellent Verilog/System Verilog programming skillsMust have previously worked on an engineering team that has taped out & successfully shipped at least one high speed processor or ASIC before.

Principal Design Verification Engineer - IO SubsystemJob Title - Principal Design Verification Engineer - IO Subsystem

SambaNova SystemsCompany Name - SambaNova Systems

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Palo Alto, California, USA

Full-time

Working at SambaNova This role presents a unique opportunity to shape the future of AI and the value it can unlock across every aspect of an organization s business and operations. We are looking for talented and motivated engineers to help us solve some of the most challenging problems in machine learning, artificial intelligence, and data analytics. As a Principal Design Verification Engineer - IO Subsystem , you'll be responsible for verifying the design, architecture, and micro-architecture

Security ArchitectJob Title - Security Architect

TechMiners LLCCompany Name - TechMiners LLC

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Remote

Contract

- Strong debugging, Analytical and problem-solving skills- Experience with UVM and ARM Bus protocols. Expertise on UVM based verification Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved

Senior ASIC / FPGA Design Verification EngineerJob Title - Senior ASIC / FPGA Design Verification Engineer

Technical LinkCompany Name - Technical Link

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Remote

Contract

6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing

ASIC Verification EngineerJob Title - ASIC Verification Engineer

Yoh - A Day & Zimmerman CompanyCompany Name - Yoh - A Day & Zimmerman Company

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Remote or Austin, Texas, USA

Full-time

ASIC Verification Engineer Reviewing the product designs and noting likely points of failure. Designing verification methodology based on product designs and failure points. Determining testing environments and verification tools. Planning the method of sequence for testing operations. Instituting and tweaking testing mechanisms and protocols. Writing up final test procedures and training QC staff. Qualificatios Bachelor s or Master s in Electrical or Computer Science 4 years of Design Verificat

ASIC RTL / SoC Design EngineerJob Title - ASIC RTL / SoC Design Engineer

TetraMem IncCompany Name - TetraMem Inc

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Fremont, California, USA

Full-time

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility. Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs. Collaborate closely with the backend team, participating in RTL coding, implementation, and synthe

ASIC Verification EngineerJob Title - ASIC Verification Engineer

Q1 Technologies, Inc.Company Name - Q1 Technologies, Inc.

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Remote or Santa Clarita, California, USA

Full-time, Contract, Third Party

Job Title : ASIC Verification Engineer Location: Bay Area, CA & Austin, Texas (Onsite only) Opening 10 Mandatory Skills: Design Verification, UVM, IP, SOC, System Verilog Job Description: Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units