Senior FPGA Verification Engineer - Data Capital Inc - Santa Clara, CA, US | Dice.com

Data Capital Inc

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Senior FPGA Verification Engineer

Santa Clara, CA, US • Posted 18 hours ago • Updated 18 hours ago

Full Time

On-site

Depends on Experience

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Job Details

Skills

FPGA
Veritas Cluster Server
verification exp
SystemVerilog
strong system verylogcoding
Verilog

Summary

3+ years of FPGA verification experience
Strong SystemVerilog programming skills
Hands-on experience with UVM (Universal Verification Methodology)
Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)
Experience with code and functional coverage analysis
Proficient in debugging and problem-solving
Scripting experience in Python or Perl
Knowledge of Verilog and/or VHDL

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91052859
Position Id: 8807672
Posted 18 hours ago

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Santa Clara, California

•

5d ago

Develop and maintain test benches using UVM/SystemVerilog.Write and debug test cases for functional and performance validation.Identify and resolve design issues in collaboration with engineering teams.Participate in design reviews and contribute to verification strategy.Stay current with the latest verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog, UVM, and tools like QuestaSim, VCS, or Haps.Familiar with Linux and scripti

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Full-time

Depends on Experience

FPGA Verification Engineer

Santa Clara, California

•

Today

Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products. Key Responsibilities: Develop and execute comprehensive verification

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Contract

Depends on Experience

FPGA Verification Engineer

Santa Clara, California

•

21d ago

Role: FPGA Verification Engineer Duration: 12 Months Location: Santa Clara, CA Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our

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Contract, Third Party

Depends on Experience

Design Verification Engineer, FPGA

Sunnyvale, California

•

30+d ago

Job Responsibilities: Assist with the planning, architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog/UVMDevelop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functionsCollect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;Enhance your leadership skills while contributing to a dynamic DV teamCreate reusable Verification IP

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Contract

$50 - $80

Senior FPGA Verification Engineer

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Job Details

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