ASIC Design Engineer Jobs in 95050

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RTL/ASIC Design Engineer

Netwoven

San Jose, California, USA

Contract

KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project s schedule. Help to improve/automate design process. Support post-silicon product bring-up/debug. PREFERRED EXPERIENCE: 10 years' experience in RTL coding Knowledge of PCIe Gen5 and PIPE specification Kno

ASIC Design Engineer

Apple, Inc.

Cupertino, California, USA

Full-time

Summary As an ASIC Design Engineer, the individual's primary responsibility will be RTL design. This will include chip architecture definition, block/function definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs. Key Qualifications Proven track-record in digital design including RTL design experienceStrong understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back

RTL ASIC Design Engineer

Innova Solutions, Inc

San Jose, California, USA

Full-time

Innova Solutions is immediately hiring for an RTL ASIC Design Engineer. Job Title: RTL ASIC Design Engineer Location: San Jose, CA, USA Contract Duration: Full Time As an RTL ASIC Design Engineer, you will: Generate and retarget IP level tests to full chip.You would have to simulate IP tests,Debugging simulation failures to root cause them,Fixing test issues.You would have to verify design fixes. Qualified candidates should APPLY NOW for immediate consideration! Please hit APPLY to provide the

ASIC Design Engineer

BlackFern Recruitment

Milpitas, California, USA

Full-time

Job Description Front-End ASIC Design Engineer - Milpitas, CA Our client develops and delivers ASIC and SoC solutions to customers worldwide in some of the hottest technology areas. The Front-End ASIC Design Engineer will be a key person in this growing design department. Micro-architecture experience is required. Great opportunity to work on current, ongoing and upcoming new projects. Hybrid remote/onsite position. Primary responsibilities include: Support customer s design through all phases o

Senior Principal ASIC Design Engineer (Hybrid)

BAE Systems

San Jose, California, USA

Full-time

Job Description You don't see it, but it's there. Our employees work on the world's most advanced electronics - from saving emissions in the City of Lights to powering the Mars Rover to protecting the F-35 fighter jet. At Electronic Systems, you'll be among the brightest minds, working on the aerospace and defense industry's most difficult problems. Drawing strength from our differences, we're innovating for the future. And you can, too. Our flexible work environment provides you a chance to ch

Camera Imaging ASIC Design Engineer

Qualcomm Technologies

Santa Clara, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > Camera Engineering General Summary: The Multimedia Camera HW team is looking for strong ASIC design engineer for an exciting opportunity to be involved in the design of world class image and video processing blocks. As a member of team, the candidate will be responsible for the following: Collaborate with hardware/system architects to micro-architect/design HW specific to Multimedia and Camera ImageSignal Proc

Cellular ASIC Design Integration Engineer

Apple, Inc.

Sunnyvale, California, USA

Full-time

Summary Do you love crafting elegant solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design! You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. This is a high visibility and mission critical role, which provides excellent exposure to multiple VLSI design technologies and flows. It also requires close working r

ASIC/RTL Design Engineer job opportunity at Santa Clara, CA / Longmont, Colorado (Onsite/Hybrid)

Infobahn Softworld Inc.

Santa Clara, California, USA

Contract

Role Title: ASIC/RTL Design Engineer - Senior Location: Santa Clara, CA / Longmont, Colorado (Onsite/Hybrid) Duration: 12+ months contract DESCRIPTION: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ens

ASIC/RTL Design Engineer - Senior - Hybrid

VIVA USA INC

San Jose, California, USA

Contract

Title: ASIC/RTL Design Engineer - Senior Description: JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client internal IP's. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC's in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development o

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Technologies

Santa Clara, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This i

ASIC/LPDRAM Design Engineer

Object Technology Solutions, Inc.

Remote or San Jose, California, USA

Contract

Description: Understand the LPDRAM state machine and develop the hardware models for DRAM features and the related validation test bench. Develop memory controller models, including request scheduling, address mapping etc., to enable new DRAM features. Develop the automation test scripts using Python to improve the overall simulation methodologies. Develop new DRAM technology changes per the spec and the state machine and the validation test bench. Experience in System C, LPDRAM, IP Simulat

ASIC Power Engineer

Apple, Inc.

Sunnyvale, California, USA

Full-time

Summary Do you like to work on ground breaking technologies that enable amazing new products? Do you have the attention for details and love for excellence to work towards an extraordinary result? Envision what you could do here! At Apple, we believe new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Key Qualifications Hands on experience with PTPX

ASIC Power Engineer

Apple, Inc.

Cupertino, California, USA

Full-time

Summary Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC/Power architecture and design, VLS

ASIC Power Engineer

Apple, Inc.

Cupertino, California, USA

Full-time

Summary Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC/Power architecture and design, VLS

ASIC RTL / SoC Design Engineer

TetraMem Inc

Fremont, California, USA

Full-time

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility. Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs. Collaborate closely with the backend team, participating in RTL coding, implementation, and synthe

ASIC/SoC Design Verification Engineer

TetraMem Inc

Fremont, California, USA

Full-time

Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels. Develop regression strategy, methodology and tools(scripts). Define

ASIC Engineer - III

CloudZenix, LLC

Santa Clara, California, USA

Contract

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 10+ years of Hardware Engineering or related work experience. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different

RTL Design Engineer - Onsite

VIVA USA INC

Santa Clara, California, USA

Contract

Title: RTL Design Engineer - Onsite Description: JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation. EDUCATION: Bachelor's or Master's in Computer Engineering KEY RESPONSIBILITIES: Perform RTL design of di

PMU Digital Design Engineer

Apple, Inc.

Cupertino, California, USA

Full-time

Summary Join our team at Apple developing complex digital IP's for Apple's custom mixed-signal integrated circuits. We have already shipped hundreds of millions of chips into Apple's existing product lines, and are developing new chips for future product lines!As a member of our mixed-signal ASIC team, you will be responsible for crafting sophisticated digital IPs for Apple power conversion and system management IC's. You will work with the system architects, product teams, verification enginee

SoC Physical Design Engineer, Electrical Analysis

Apple, Inc.

Sunnyvale, California, USA

Full-time

Summary Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies