ASIC Verification Engineer Jobs

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ASIC Engineering Technical Lead- DFT

Cisco Systems, Inc.

San Jose, California, USA

Full-time

The application window is expected to close on 4/25/25 This is an onsite role and will require working out of the Milpitas/San Jose office Meet the Team: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way thr

ASIC Design Leader

Kratos Defense and Security Solutions, Inc.

Crane, Indiana, USA

Full-time

Job Description Permanent Residents and Visa-holders are not eligible for employment. General Summary This full-time position is in the Systems Development Department of Kratos SRE and is a highly motivated and self-driven role that will focus on leading development efforts for next-generation technologies for microelectronics Key Responsibilities Provide technical leadership in the development and evaluation of custom integrated circuit designs for defense applications,Investigate, research

ASIC STA & CAD Engineering

Coretek Labs

Longmont, Colorado, USA

Full-time, Contract, Third Party

Job Title: ASIC STA & CAD Engineering Location: Longmont, Colorado (Hybrid) Duration: Long Term Contract Rate: $50-60/hr. Domain: Engineering Key Responsibilities: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Engaging closely with block and SoC design teams to under

Senior Manager / ASIC STA & CAD Engineering

Coretek Labs

Longmont, Colorado, USA

Contract, Third Party

Job Title: ASIC STA & CAD Engineering Location: Longmont, Colorado (Hybrid) Duration: Long Term Contract Domain: Engineering Key Responsibilities: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Engaging closely with block and SoC design teams to understand the design