JEDEC Jobs in San Diego, CA

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Validation Engineer with DDR Familiarity

Qualcomm Technologies

•

San Diego, California, USA

Full-time

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. Qualcomm's Silicon Validation team is part of the central SoC digital hardware organization responsible for the overall quality of the SoC si
Posted 40 days ago | Updated 4 hours ago

Engineer|6117 Engineer|6117

ACL Digital

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San Diego, California, USA

Full-time

Job Description: Top 5 Required Skills (These are not preferred skills. If the candidate does not have these required skills, they will be rejected completely) Familiarity with DDR interface, JEDEC spec, bus level view of transactions Regression and PVT testing Emulation Build Validation Potency in reading C code, understanding code flow, code manipulation, and test iteration. Technologies: C Programming Required Education: Bachelor's degree in Computer Science, Electrical/Electronics Engineeri
Posted 60+ days ago | Updated 4 hours ago

Signal and Power Integrity Engineer (Multiple Locations)

Qualcomm Technologies

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San Diego, California, USA

Full-time

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (
Posted 60+ days ago | Updated 4 hours ago

DV Engineers DDR (either IP or SoC level experience)- Remote

E-Solutions, Inc.

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California, USA

Full-time, Third Party, Contract

Role: DV Engineers DDR (either IP or SoC level experience) Work Location: USA (Remote) Experience: 10+ Years Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own f