Sr. FPGA Board Electrical Engineer Jobs in Pleasanton, CA

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Hardware Security, Senior Principal Developer

Oracle Corporation

Santa Clara, California, USA

Full-time

Job Description Oracle Cloud Infrastructure (OCI) is seeking a highly driven hardware security expert at the Senior Principal Engineer level. The individual in this role will lead and drive the hardware security architecture and related design aspects of the teams developing cutting edge hardware systems and solutions for Oracle's growing Cloud and flagship enterprise solutions. The Oracle Hardware Development organization you will join has delivered the first and second generation of Oracle cl

Firmware Developer(ROT)

3S Business Corporation Inc.

Remote

Full-time, Part-time, Third Party, Contract

Firmware Developer Redmond-Microsoft Remote (PST) Please share profiles on from PST time zone 1. Production quality (in Unit Tested environment) in C for Root of Trust (RoT) Firmware development, SoC bring-up, bootloaders, platform initialization, board support package porting, crypto library porting, peripherals such as PCIe, NVMe, I2C, SPI, USB, UART, and I3C. 2. Design and implement specifications for cutting edge features related to security. Stress on modular design and code reuse to ach

ASIC RTL / SoC Design Engineer

TetraMem Inc

Fremont, California, USA

Full-time

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility. Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs. Collaborate closely with the backend team, participating in RTL coding, implementation, and synthe

ASIC Verification Engineer

Technical Link

Santa Clara, California, USA

Full-time

Job Description Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. Responsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure.Job Requirements 15+ year

ASIC Verification (Fulltime)

Technical Link

Remote

Full-time

Job Description Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. esponsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure.Job Requirements 15+ years

Full-Time Positions - RTL Designer engineer (100% remote considered), to work with a company at the forefront of hardware technologies accelerating and optimizing FHE encryption via Artificial Intelligence.

VortexLink

Remote

Full-time

Senior RTL Designer Engineer. Full-time opportunity inCampbell, CA(100% remote considered). Responsibilities Develop and execute: micro-architecture specification, RTL in Verilog/System Verilog, performance, speed, power goals, and verificationBringing up the chip in lab and developing bring-up scriptsParticipate in chip architecture definition, review, verification, and testingRequirements BS/MS in Electrical Engineering or Computer Engineering with 5+ years of relevant experience from design