VCS Jobs in San Jose, CA

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RTL Engineer

Cloudious

Santa Clara, California, USA

Contract

Title: RTL Engineer Location: Santa Clara, CA (Day-1 onsite) Duration: 6 Months Role: Integrate RISC-V Core to SoC Key Responsibilities Integrate RISC-V CPU cores into SoC designs, collaborating with cross-functional teams (DV, physical design, architecture, verification, and post-silicon validation) to ensure seamless delivery. Develop and optimize RTL (using Verilog/SystemVerilog) for core, interconnect, and memory subsystems. Evaluate and integrate third-party IP, ensuring performance, power,

Principal Verification Engineer

OSI Engineering, Inc.

San Jose, California, USA

Full-time

A leading chip and silicon IP provider is seeking a talented Principal Verification Engineer to join its Memory Interconnect Design team. In this full-time hybrid role, youll work alongside world-class engineers to develop advanced technologies that make data faster and more secure. As a key technical leader in the organization, the Principal Verification Engineer will be responsible for defining and executing verification strategies across multiple product lines and global sites. The ideal can

VDI Engineer

Synapse Business Systems

Remote

Contract, Third Party

Job Title: Lead / Senior VDI Engineer Omnissa Horizon Location: RemoteOnly for NY, NJ, CT, PA- Do apply Department: Core Infrastructure VCS Operations Reports To: Manager VCS OperationsKey Responsibilities:Lead the design, deployment, and lifecycle management of Omnissa Horizon environmentsDrive migration efforts from legacy VDI platforms (e.g., Moonshot, Nutanix) to HorizonIntegrate Horizon with Workspace ONE, Active Directory, and endpoint toolsProvide Tier 3 support and root cause analysis f

DV Engineers DDR (either IP or SoC level experience)- Remote

E-Solutions, Inc.

California, USA

Full-time, Contract, Third Party

Role: DV Engineers DDR (either IP or SoC level experience) Work Location: USA (Remote) Experience: 10+ Years Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own f