Verification Engineer Jobs

41 - 60 of 182 Jobs

Verification EngineerJob Title - Verification Engineer

AdientOne LLCCompany Name - AdientOne LLC

•

Massachusetts, USA

Contract

Role: Verification Engineer Location: Boxborough MA 01719 | Hybrid Duration: 12+ months Note: Prefer experience with PSS language and UVM Job Description: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and ove

ASIC Design Verification EngineerJob Title - ASIC Design Verification Engineer

Verito SolutionsCompany Name - Verito Solutions

•

San Francisco, California, USA

Contract

We are seeking a highly skilled and motivated ASIC Design VerificationEngineer with over 6 years of experience in the field of verification. As an Individual Contributor, he/she will play a crucial role in ensuring the quality and reliability of our cutting-edge ASIC designs, contributing to industry-leading innovations. Key Responsibilities: Develop and implement test plans, test cases, and coverage metrics for ASICverification.Perform block-level and chip-level verificationProficiency in Syste

Staff Systems Verification EngineerJob Title - Staff Systems Verification Engineer

Abbott LaboratoriesCompany Name - Abbott Laboratories

•

Pleasanton, California, USA

Full-time

Abbott is a global healthcare leader that helps people live more fully at all stages of life. Our portfolio of life-changing technologies spans the spectrum of healthcare, with leading businesses and products in diagnostics, medical devices, nutritionals and branded generic medicines. Our 114,000 colleagues serve people in more than 160 countries. Job Title Staff Systems Verification Engineer Working at Abbott At Abbott, you can do work that matters, grow, and learn, care for yourself and fa

Junior verification engineerJob Title - Junior verification engineer

Realtime Associates LtdCompany Name - Realtime Associates Ltd

•

Jersey City, New Jersey, USA

Full-time

Job Title: Junior Verification Engineer Location: New Jersey Job Type: Contractor About AirSpanAirSpan is seeking a motivated Junior Verification Engineer to contribute to the validation and testing of FPGA designs. This role offers an opportunity to develop expertise in Universal Verification Methodology (UVM) and SystemVerilog while working alongside experienced engineers in a collaborative environment. Job DescriptionAs a Junior UVM SystemVerilog Verification Engineer, you will support the de

Verification EngineerJob Title - Verification Engineer

Mice GroupsCompany Name - Mice Groups

•

Sunnyvale, California, USA

Contract

Mandatory Experience: 7 + years experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycleExperience in the development of UVM based verification environments from scratchExperience with Design verification of Data-center applications like Video, AI/ML, and Networking designsMinimum Qualifications B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer ScienceHands-on experience in Verilog, System Verilog, C/

Design Verification EngineerJob Title - Design Verification Engineer

LeadStack, Inc.Company Name - LeadStack, Inc.

•

No location provided

Full-time, Contract

Lead Stack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world. TITLE: Design Verification Engineer LOCATION: San Jose CA/ Austin TX DURATION: 5+ Months with possible extension Rate: $90-$110/hr on W2 Job Descriptio

System IP Design Verification EngineerJob Title - System IP Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

•

Austin, Texas, USA

Contract

Job Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX, USA / San Jose, CA (Hybrid) Note: GLS verification experience, preferably on SoC designs." Good hands-on experience in debugging GLS. Must Have: Minimum 10 years of experience in verification of DV role along withHands on UVM, system Verilog and TestbenchGate Level simulation Primary skillsRTL designMajority of work will be on Gate level simulationThis will be a ands on roleNice to have: LPDDR memoryco

Senior FPGA Design Verification Engineer - Secret ClearanceJob Title - Senior FPGA Design Verification Engineer - Secret Clearance

Amarx Search, Inc.Company Name - Amarx Search, Inc.

•

Dedham, Massachusetts, USA

Full-time

Amarx Search, Inc. - amarx.com Direct Hire - Full Time position in Dedham, MA Position ID: 2632 An excellent position with a major global technology solutions company * Senior FPGA Design Verification Engineer - Secret Clearance * Please apply ONLY if you have an active DOD Secret clearance and VHDL (or similar) United States Citizenship is required due to government contract requirement; we are unable to sponsor at this time. We can ONLY consider your application if you have: 1: Active DOD Sec

Firmware Verification/Test Engineer (Blackbox)Job Title - Firmware Verification/Test Engineer (Blackbox)

Oxford Global ResourcesCompany Name - Oxford Global Resources

•

Burnsville, Minnesota, USA

Contract

Title : Firmware Verification / Test Engineer (Blackbox) Location: Burnsville, MN OR Lincoln, NE 100% ONSITE. Preference is on local, will look at Nationals if a perfect fit Length of Contract: 8 Months Start: as early as 5/12 if we can get someone there They will need figure out what test cases need to be written, write the test case and then will be running / executing the test case and then integrating them into Azure Skills Required: Firmware Verification/Test/Requirements Linux Familiar wit

Verification and Validation EngineerJob Title - Verification and Validation Engineer

Rose InternationalCompany Name - Rose International

•

Plymouth, Minnesota, USA

Full-time

Date Posted: 05/01/2025 Hiring Organization: Rose International Position Number: 482096 Job Title: Verification and Validation Engineer Job Location: Plymouth, MN, USA, 55441 Work Model: Onsite Shift: Onsite Employment Type: Temporary Estimated Duration (In months): 10 Min Hourly Rate($): 50.00 Max Hourly Rate($): 55.00 Must Have Skills/Attributes: Drawing, MATLAB, Medical device, Python, Validation Job Description Required Education & Experience Bachelor's degree in Electrical, Mechanica

Mixed Signal Verification EngineerJob Title - Mixed Signal Verification Engineer

Everest Consultants, IncCompany Name - Everest Consultants, Inc

•

Hillsboro, Oregon, USA

Full-time

Job Title: Mixed Signal Verification Engineer Duration: Permanent, Full-time Location: Hillsboro, OR (Hybrid: onsite 3 days per week) Pay Range: $101,000 to $170,000 per year **Candidates must have valid U.S. work authorization at the time of hire. Our client, a leader in the test-and-measurement and wireless communications industries, is seeking passionate individuals with a vision for the future, a desire to make an impact, and a drive to turn innovative ideas into reality. They are building d

Design Verification EngineerJob Title - Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

•

Austin, Texas, USA

Contract

Title - System IP Design Verification Engineer Duration 6+ Months Job ID - 429704 Location - 3900 N Capital of Texas Hwy, Austin, TX, USA OR 3655 N 1st St, San Jose, CA, USA Job Description As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification

FPGA Design Verification EngineerJob Title - FPGA Design Verification Engineer

DBA Web TechnologiesCompany Name - DBA Web Technologies

•

Dedham, Massachusetts, USA

Full-time

FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl, TCL, Python, VHDL, Xilinx FPGA & Questa) in Dedham, MA7+ to 10 years of experience POSITION: FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl, TCL, Python, VHDL, Xilinx FPGA & Questa) in Dedham, MA SECURITY CLEARANCE: Must be able to obtain Secret Security Clearance (ship is Required) LOCATION: Dedham, MA (onsite) DURATION: Full-Time Positio

Design Verification EngineerJob Title - Design Verification Engineer

Avance ConsultingCompany Name - Avance Consulting

•

Remote

Full-time

<>Key Responsibilities:Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely with RTL designers to resolve issuesExecute regressio

Design Verification EngineerJob Title - Design Verification Engineer

TecHobbitCompany Name - TecHobbit

•

Remote

Contract

Title: Design Verification Engineer Location: Remote Duration: 12 months with possible extension Requirement: Good Design Verification Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis &

Lead Formal Verification EngineerJob Title - Lead Formal Verification Engineer

Mindsource IncCompany Name - Mindsource Inc

•

Sunnyvale, California, USA

Contract

Title: Lead Formal Verification Engineer Location: Sunnyvale, CA (or) Austin, TX Duration: Long-term Type: Contract (W2/C2C) Rate: $110-$130/hr Responsibilities: Provide technical leadership in Formal Verification Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level Work with Architecture and Design team to come up with Formal driven specification and implementation Define formal verification scope, develo

Senior Validation and Verification (V&V) EngineerJob Title - Senior Validation and Verification (V&V) Engineer

EmersonCompany Name - Emerson

•

Austin, Texas, USA

Full-time

JOB DESCRIPTION Job Summary Emerson's Test and Measurement Systems group (formerly known as NI) Product R&D has an immediate opening for a Senior V&V Engineer within our Integrated Products design team in Austin, TX In this role, you will have the opportunity to work throughout the product lifecycle to develop products and systems that expand the test and measurement industry's capabilities. V&V engineers within our Test and Measurement Systems business group are a key part of ensuring new des

Design Verification EngineerJob Title - Design Verification Engineer

Innova Solutions, IncCompany Name - Innova Solutions, Inc

•

Remote or Mountain View, California, USA

Contract, Third Party

A client of Innova Solutions is looking for an Design Verification Engineer. Position type: Contract Duration: 12+ Months Location: Mountain View, CA (Onsite Job) As a Design Verification Engineer, you will need: Minimum Qualifications: Experience in SV and UVM and good debugging skills.Understanding of AMBA protocols.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/co

Mixed-Signal Design Verification EngineerJob Title - Mixed-Signal Design Verification Engineer

Talent Junction, LLC.Company Name - Talent Junction, LLC.

•

San Jose, California, USA

Third Party, Contract

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

Junior Verification EngineerJob Title - Junior Verification Engineer

GlobalLogic Inc.Company Name - GlobalLogic Inc.

•

Warren, New Jersey, USA

Third Party, Contract

Job Description: Assist in developing and implementing UVM-based verification plans for FPGA designs.Perform functional and regression testing for digital hardware components.Develop and maintain test benches, test cases, and automation scripts in System Verilog.Analyze test results, debug issues, and collaborate with senior engineers to resolve defects.Ensure compliance with industry standards and customer requirements.Document test procedures, results, and defect tracking.Continuously learn an