hardware digital: rtl design Jobs

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Senior Software Engineer- Core and Test Infrastructure

Aduril Industries

Costa Mesa, California, USA

Full-time

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and c

Senior Linux System Administrator

General Dynamics Information Technology

Livermore, California, USA

Full-time

Type of Requisition: Regular Clearance Level Must Currently Possess: Top Secret/SCI Clearance Level Must Be Able to Obtain: Top Secret SCI + Polygraph Public Trust/Other Required: None Job Family: Systems Administration Job Qualifications: Skills: Linux, Microsoft Server Operating Systems, Microsoft Windows Environment Certifications: None Experience: 8 + years of related experience ship Required: Yes Job Description: $10K Sign-on bonus A Senior Linux System Administrator Maintains an

Industrial Engineer

Aduril Industries

Costa Mesa, California, USA

Full-time

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and c

Senior Linux System Administrator

General Dynamics Information Technology

Livermore, California, USA

Full-time

Type of Requisition: Regular Clearance Level Must Currently Possess: Top Secret/SCI Clearance Level Must Be Able to Obtain: Top Secret SCI + Polygraph Public Trust/Other Required: None Job Family: Systems Administration Job Qualifications: Skills: Linux, Microsoft Server Operating Systems, Microsoft Windows Environment Certifications: None Experience: 8 + years of related experience ship Required: Yes Job Description: $10K Sign-on bonus A Senior Linux System Administrator Maintains an o

SDC Engineer ( Fullchip timing / SDC development, Static Timing Analysis )

Wise Equation Solutions Inc.

San Jose, California, USA

Third Party, Contract

Position: SDC Engineer Location: San Jose CA (Day-1 Onsite) Long Term Contract SDC:/Design Constraints and STA: Timing Analysis (PrimeTime) : Very good knowledge in writing Timing Constraints with these tools Digital Circuits: Person should be very strong in Design Fundamentals so can make right changes in RTL as neededBridge: He needs to act as a bridge between Design & Physical Design team and provide solutions to meet timings through constraints PD Tools: Nice to have but not must have floor

OEM Field Engineer II

Panasonic

North Charleston, South Carolina, USA

Full-time

Overview Who we are: Ever wonder who brings the entertainment to your flights? Panasonic Avionics Corporation is #1 in the industry for delivering inflight products such as movies, games, WiFi, and now Bluetooth headphone connectivity! How exciting would it be to be a part of the innovation that goes into creating technology that delights millions of people in an industry that's here to stay! With our company's history spanning over 40 years, you will have stability, career growth opportunities

Principal UVM Digital Verification Engineer

BlackFern Recruitment

Cambridge, Massachusetts, USA

Full-time

Security clearance: Applicants selected for this position will be required to obtain and maintain a government security clearance Our Digital Design Team is seeking a motivated and experienced Principal UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and commun

Senior Design Verification Engineer

Sivaltech

San Diego, California, USA

Contract

Job descriptionCompany Description Sivaltech is a well-established ASIC/FPGA, Analog, and Embedded Software design services company with offices in California, USA, and Bangalore, India. We are a preferred design services partner for both Fortune 500 companies and startups in the semiconductor industry. With expertise spanning GPUs, CPUs, wireless, communications, medical, broadband, and consumer electronics, Sivaltech is well-equipped to address our clients' complex design challenges. Role Desc

STA Engineer

Cybotic Systems LLC

San Jose, California, USA

Contract

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop efficient methodolog

AI HW Design Verification Engineer

Yoh - A Day & Zimmerman Company

Remote or Santa Clara, California, USA

Full-time

AI HW Design Verification Engineer Looking for a Senior Design Verification Engineer. This person will play a key role in quality and reliability of digital designs through comprehensive verification methodologies. This person should have a strong background in verification techniques/processes, problem solving skills, and skilled at delivering high quality designs. Scope: Develop & execute comprehensive verification strategies in order to validate complex digital designs, ensuring compliance w

Design Verification Engineer

Mirafra Inc

San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Network Manager

GovCIO

Sumter, South Carolina, USA

Full-time

Overview GovCIO is currently hiring for a Network Manager . This position will be located in Sumter, SC and will be an onsite position. Responsibilities Provide network operations. The contractor shall: Use AFCENT provided standard network devices for routing and switching; Operate, maintain and sustain IP based routers, switches and standard AFCENT approved operating systems on AFCENT network devices; Configure Tier 2 routing and switching devices IAW SPIN-C.; Design and implement solutio

Sr ASIC/FPGA VHDL Design Engineer Secret Clearance Required No Sponsorship Available

ZoeTech Staffing LLC

Camden, New Jersey, USA

Full-time

Schedule: 9/80 Regular with every other Friday off Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols. The company has state-of-the-art EDA flows/

Silicon Verification Engineer 2

Dexian DISYS

Remote

Contract

Role: Silicon Verification Engineer 2 Location: 100% remote Duration: Till 9/30/2025 (Possible Extension : Yes) Summary: The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans. Job Responsibilities: Define, document, and implement a UVM verification environment including agents and scoreboards Write test plans and implement them by developing tests, test generators, test benches, che

Design Verification Engineer

Innova Solutions, Inc

Mountain View, California, USA

Contract

A client of Innova Solutions is immediately hiring for a Design Verification Engineer Position type: Contract Location: Mountain View, CA-Onsite As a Design Verification Engineer, you will be responsible for: Job description: Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirements.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC leve

Senior VLSI Physical Design Engineer

APN Software Services, Inc

Irvine, California, USA

Full-time

Please contact Abdul on "" OR email me at "" We are seeking a highly skilled Senior SoC/ASIC Physical Design Engineer to lead and drive the physical design activities to successful closure by collaborating closely with RTL and other cross-functional engineering teams. You will be responsible for developing, refining and implementing cutting-edge flows and methodologies that optimize design performance, power efficiency, and area (PPA). Your expertise will directly contribute to achieving world-c

Sr SoC Gate-Level Simulation (GLS) Engineer

Yoh - A Day & Zimmerman Company

Remote or Santa Clara, California, USA

Full-time

Sr SoC Gate-Level Simulation (GLS) Engineer In need of a solid Gate-Level Simulation Engineer to support complex System-on-Chip (SoC) development. In this contract role, you ll be responsible for verifying gate-level functionality, timing, and power across SoC subsystems. You'll work closely with RTL, physical design, and verification teams to ensure accurate coverage and system-level stability. Scope: Develop and apply GLS methodologies for high-performance SoC projects Run gate-level simulati

DFT/DFD Verification Engineer - Advanced SoC Projects

Yoh - A Day & Zimmerman Company

Remote or Santa Clara, California, USA

Full-time

DFT/DFD Verification Engineer Advanced SoC Projects We are looking for a seasoned Design-for-Test / Design-for-Debug Verification Engineer focused on validating sophisticated test and debug logic within next-generation SoCs. This position involves verifying scan architectures such as JTAG, iJTAG, and other internal debug features to support robust manufacturing testability and effective post-silicon debugging. The role will require tight collaboration with engineering teams across design, integ

JEMINI Network Engineer

Judge Group, Inc.

Colorado Springs, Colorado, USA

Full-time

Location: Colorado Springs, CO Salary: $65.00 USD Hourly - $75.00 USD Hourly Description: Our client is currently seeking a JEMINI Network Engineer based out in Colorado Springs, CO. ONLY W2 This job will have the following responsibilities: The network engineer will produce designs including system, logical, and connectivity drawings using DoDAF standards and present them to different engineering review boards. Conducts testing of network design. Maintains technical expertise in all areas

Senior Cybersecurity Engineer

Penn Medicine

Philadelphia, Pennsylvania, USA

Full-time

Description Penn Medicine is dedicated to our tripartite mission of providing the highest level of care to patients, conducting innovative research, and educating future leaders in the field of medicine. Working for this leading academic medical center means collaboration with top clinical, technical and business professionals across all disciplines. Today at Penn Medicine, someone will make a breakthrough. Someone will heal a heart, deliver hopeful news, and give comfort and reassurance. Our e