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Lead Formal Verification Engineer

Mindsource Inc

Sunnyvale, California, USA

Contract

Title: Lead Formal Verification Engineer Location: Sunnyvale, CA (or) Austin, TX Duration: Long-term Type: Contract (W2/C2C) Rate: $110-$130/hr Responsibilities: Provide technical leadership in Formal Verification Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level Work with Architecture and Design team to come up with Formal driven specification and implementation Define formal verification scope, develo

Design Verification Engineer

Yoh - A Day & Zimmerman Company

Remote or Santa Clara, California, USA

Full-time

Design Verification Engineer Scope: Design and development of the IO subsystems for a high-performance SoC from scratch, working closely with the Architecture and RTL teams. Develop detailed block-level design specifications and plans for a high-performance IO Subsystem. Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers. Develop and optimize the IO subsystem design to ensure functionality and performance are in a

ASIC/FPGA Design Engineer, 5+ Years

Lockheed Martin Corporation

Remote or California, USA

Full-time

Job Description Join Our Team as an ASIC & FPGA Design Engineer where you will support over 50 different programs and research and development (R&D) efforts, affecting technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions. Location: Although this position does support some teleworking; the selected candidate will need to be located near our Lockheed Martin Space f

ASIC Verification Engineer

Yoh - A Day & Zimmerman Company

Remote or Monte Sereno, California, USA

Full-time

ASIC Verification Engineer Reviewing the product designs and noting likely points of failure. Designing verification methodology based on product designs and failure points. Determining testing environments and verification tools. Planning the method of sequence for testing operations. Instituting and tweaking testing mechanisms and protocols. Writing up final test procedures and training QC staff. Qualificatios Bachelor s or Master s in Electrical or Computer Science 4 years of Design Verificat