systemverilog Jobs

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Onsite Mid-level Verification Engineer, UVM, SystemVerilogJob Title - Onsite Mid-level Verification Engineer, UVM, SystemVerilog

Intelliswift Software IncCompany Name - Intelliswift Software Inc

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Newark, California, USA

Contract

Mid-level Verification Engineer with 5-8 years of experience of pure verification in FPGA. This is a pure Verification Engineer role. This position is onsite in the greater San Jose Bay Area. What you will be doing: Purely verification of FPGAProgramming using SystemVerilogDevelop OO testbench infrastructureDevelop test cases using UVMScripting What you will need: 5-8 years in pure VerificationSolid in SystemVerilog programmingExperience with UVM, Universal Verification MethodologyExperience

Senior ASIC & FPGA Design EngineerJob Title - Senior ASIC & FPGA Design Engineer

Triple Crown ConsultingCompany Name - Triple Crown Consulting

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Orlando, Florida, USA

Contract

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth. CONTRACT Position: 12 Months Location: Onsite in Orlando, FL Candidate must be authorized to work in the US We are seeking a highly skilled ASIC & FPGA Design Engineer to join o

RTL Engineer: Integrate RISC-V Core to SoCJob Title - RTL Engineer: Integrate RISC-V Core to SoC

Intelliswift Software IncCompany Name - Intelliswift Software Inc

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Santa Clara, California, USA

Contract

Job Title: RTL Engineer: Integrate RISC-V Core to SoC Location(s): Santa Clara, CA - Onsite Must Have skills: 5+ years of experience in RTL design, SoC integration, or related areas.Strong hands-on experience with hardware description languages (Verilog, SystemVerilog, VHDL), EDA tools, and simulators (VCS, NC, Verilator).Deep understanding of SoC design, integration, and high-performance interfaces (e.g., AXI, TileLink, PCIe, Ethernet).Proven ability to debug and optimize designs for functiona

ASIC Engineer, Formal VerificationJob Title - ASIC Engineer, Formal Verification

VeearCompany Name - Veear

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Sunnyvale, California, USA

Contract

Requirements: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.5+ years of experience in Formal VerificationExperience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etcProven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniquesProven analytical skills to craft Client solutions to tackle industry-le

Senior Design Verification Engineer-12+Yrs Candidate neededJob Title - Senior Design Verification Engineer-12+Yrs Candidate needed

SivaltechCompany Name - Sivaltech

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San Diego, California, USA

Contract, Third Party

Job Title: Senior Design Verification Engineer Company: Sivaltech Location: San Diego, CA Job Type: Full-time About Sivaltech: Sivaltech is a leading technology company driving innovation and excellence in the industry. We're seeking an experienced Senior Design Verification Engineer to join our team in San Diego, CA. Job Description: As a Senior Design Verification Engineer, you'll develop and execute verification plans for complex digital designs, working closely with cross-functional teams to

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Embedded Systems Team ManagerJob Title - Embedded Systems Team Manager

NsightCompany Name - Nsight

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Santa Clara, California, USA

Contract

10+ years engineering management / engineering contracting experience, minimum 3 years of embedded. 2+ years experience with Jira Certified Scrum Master (or equivalent experience) Able to review code, track productivity metrics, refine requirements and report to stakeholders C, C++, Python fluent. 2 years experience with at least one of the following: OpenBMC/YoctoLinux, PetaLinux, or Zephyr. At least one successful product bringup involving either a custom ASIC or FPGA based logic. Alternativel

System IP Design Verification EngineerJob Title - System IP Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

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Austin, Texas, USA

Contract

Title: Senior System IP Design Verification Engineer (Contract)Duration: Through 09/12/2025Pay: $90/hr $120/hr Job OverviewWe're looking for a Senior Staff System IP Design Verification Engineer to lead verification efforts for advanced System IP (coherent interconnects, caches). This is a hands-on role requiring deep experience in UVM, SystemVerilog, and gate-level simulation (GLS). Key ResponsibilitiesDevelop reusable testbenches and verification environments from scratch Drive best practices

Design Verification EngineerJob Title - Design Verification Engineer

SivaltechCompany Name - Sivaltech

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Santa Clara, California, USA

Contract, Third Party

Job Title: Design Verification Engineer (DV) Company: Sivaltech Location: Santa Clara, CA Job Type: Full-time About Sivaltech: Sivaltech is a leading technology company driving innovation in the industry. We're seeking an experienced Design Verification Engineer to join our team in Santa Clara, CA. Job Description: As a Design Verification Engineer, you'll develop and execute verification plans for complex digital designs, focusing on Ethernet PHY or PCS. You'll work closely with cross-functiona

Silicon Design Verification Engineer IIIJob Title - Silicon Design Verification Engineer III

Ascendion Inc.Company Name - Ascendion Inc.

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Burlingame, California, USA

Full-time

About Ascendion Ascendion is a full-service digital engineering solutions company. We make and manage software platforms and products that power growth and deliver captivating experiences to consumers and employees. Our engineering, cloud, data, experience design, and talent solution capabilities accelerate transformation and impact for enterprise clients. Headquartered in New Jersey, our workforce of 11,000+ Ascenders delivers solutions from around the globe. Ascendion is built differently to e

Design Verification EngineerJob Title - Design Verification Engineer

VeearCompany Name - Veear

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Sunnyvale, California, USA

Contract

Requirements: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.Hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.Experience in EDA tools and scripting (Pytho

ASIC Engineer (Design Verification)Job Title - ASIC Engineer (Design Verification)

CloudiousCompany Name - Cloudious

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Sunnyvale, California, USA

Third Party, Contract

ASIC Engineer (Design Verification) Bay Area, CA or Austin, TX 12 Months Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collab

FPGA Design EngineerJob Title - FPGA Design Engineer

GlobalLogic Inc.Company Name - GlobalLogic Inc.

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Warren, New Jersey, USA

Third Party, Contract

Job Description: You will innovate in 4G, 5G, and O-RAN systems in a competitive atmosphere.Experience in FPGA design and development.Proficiency in Verilog/SystemVerilog for digital logic design.Experience with FPGA development tools such as Xilinx Vivado, and Intel Quartus.Knowledge of wireless communication systems, 4G/5G networks, and O-RAN architectures.Strong understanding of DSP algorithms and their FPGA implementations.Experience in debugging in the lab using Vivado ILAs and experience

System Verilog UVM Design Verification Test EngineerJob Title - System Verilog UVM Design Verification Test Engineer

U.S. Tech Solutions Inc.Company Name - U.S. Tech Solutions Inc.

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Goleta, California, USA

Contract

Job Description: The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data. Responsibilities: UVM/python test development for driving VIPs and other stimulus driversGeneration of test components such as monitors, scoreboards and python modelsCoverage closure and GLS bringup and testing Experience: 6+ years of experience with verification methodologies

Design Verification EngineerJob Title - Design Verification Engineer

AdientOne LLCCompany Name - AdientOne LLC

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Massachusetts, USA

Contract

Role: Design Verification Engineer Location: Boxborough MA 01719 | Hybrid Duration: 7 months Job Description: Collaborate with team to verify complex IP blocks. Develop and execute tests. Debug issues related to functionality, performance, and power. Work on functional and/or code coverage closure. Requirements: Proven experience working in UVM and constrained-random simulation environments. Strong knowledge of System Verilog, Verilog, C/C++, and scripting languages. Familiarity with 3D pipelin

ASIC & FPGA Design EngineeringJob Title - ASIC & FPGA Design Engineering

Judge Group, Inc.Company Name - Judge Group, Inc.

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Orlando, Florida, USA

Full-time

Location: Orlando, FL Description: Role - Asic & Fpga Design Engineering Type: Contract Location - ( Onsite) Job Description: Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses spe

ASIC/FPGA Verification Engineer, 5+ YearsJob Title - ASIC/FPGA Verification Engineer, 5+ Years

Lockheed MartinCompany Name - Lockheed Martin

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Denver, Colorado, USA

Full-time

Job ID: 690704BR Date posted: Apr. 04, 2025 Description:Join Our Team as an ASIC & FPGA Verification Engineer where you will support over 50 different programs and research and development (R&D) efforts, affecting technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions. Location: Although this position does support some teleworking; the selected candidate will need

R&D Engineer IC DesignJob Title - R&D Engineer IC Design

Broadcom CorporationCompany Name - Broadcom Corporation

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San Jose, California, USA

Full-time

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Engineer will be responsible for verification of complex switch designs. Responsibilities will include creating SystemVerilog-based verification environments (testbenches, checkers, transactors) as well as creating and executing testplans for verificat

Verification EngineerJob Title - Verification Engineer

AdientOne LLCCompany Name - AdientOne LLC

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Massachusetts, USA

Contract

Role: Verification Engineer Location: Boxborough MA 01719 | Hybrid Duration: 12+ months Note: Prefer experience with PSS language and UVM Job Description: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and ove

Design Verification Engineer at Santa Clara, CA (Hybrid)Job Title - Design Verification Engineer at Santa Clara, CA (Hybrid)

Infobahn Softworld Inc.Company Name - Infobahn Softworld Inc.

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Santa Clara, California, USA

Contract, Third Party

Role Title: Design Verification Engineer Location: Santa Clara, CA, 95054 (Hybrid 3 days a week) Duration: 12+ months contract Job Duties: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the