Remote
•
Today
Role: FPGA Validation Engineer Location: Santa Clara, CA (Onsite) Skills: VHDL, Verilog, Hardware Description Languages (HDL), UVM (Universal Verification Methodology) and OVM (Open Verification Methodology), DSP, Python and TCL, Xilinx (Vivado) and Intel (Quartus) Roles & Responsibilities: Validating and implementing digital circuits using FPGA technologyTesting and debugging designs to ensure they meet requirementsCollaborating with other engineers and stakeholders to ensure designs meet proj
Easy Apply
Contract, Third Party
Depends on Experience