RTL Design Engineer Jobs

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RTL Design

HCL America Inc.

On-site in Sunnyvale, California, USA

Full-time

RTL Design Sunnyvale, CA Have in depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, timing and formal verificationProficiency of Verilog or SystemVerilogExperience with multi-clock domain designsExperience in ASIC/IP developmentDesign knowledge of data processing, encoder/decoders, arbitration algorithms, protocol designs and display related standards etc.Strong in both written and verb

RTL Design engineer with strong experince on PCIe

Della Infotech

On-site in San Jose, California, USA

Contract, Third Party

Position: RTL Design engineer with strong experince on PCIe Location: San Jose, CA / Irvine, CA / Austin, TX Onsite Duration: 06 Months Candidate Roles and Responsibilities PCIe System Expertise:Deep understanding and hands-on experience in PCIe system architecture, with an emphasis on physical layer design and specification.Ensure compliance with PCIe specifications, including but not limited to PIPE interface, LTSSM, 8b/10b and 128b/130b encoding, EIEOS intervals, equalization and electrical i

ASIC/RTL Design Engineer job opportunity at Santa Clara, CA / Longmont, Colorado (Onsite/Hybrid)

Infobahn Softworld Inc.

On-site in Santa Clara, California, USA

Contract

Role Title: ASIC/RTL Design Engineer - Senior Location: Santa Clara, CA / Longmont, Colorado (Onsite/Hybrid) Duration: 12+ months contract DESCRIPTION: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ens

RTL Design Engineer

SGS Consulting

Hybrid in Santa Clara, California, USA

Contract

THE DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client s internal IPs.Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micr

ASIC/RTL Design Engineer - Senior - Hybrid

VIVA USA INC

Hybrid in San Jose, California, USA

Contract

Title: ASIC/RTL Design Engineer - Senior Description: JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client internal IP's. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC's in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development o

RTL Design Engineer - Hybrid

VIVA USA INC

Hybrid in San Jose, California, USA

Contract

Title: RTL Design Engineer Description: KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project s schedule. Help to improve/automate design process. Support post-silicon product bring-up/debug. PREFERRED EXPERIENCE: Knowledge of PCIe Gen5 and PIPE specificatio

FPGA/RTL Design Engineer

Ampcus Inc

Remote

Contract

Title: Engineer: FPGA/RTL Design - Location: Hillsboro, OR - Remote position Expected Duration: 04/01/2024 to 12/31/2024 Job Description: 100% remote Laptop will be issued RTL Design and Verification Job Description: The hire will be involved in deep sub-micron IC logic and VLSI design, validation, development, developing, verifying, and validating competitive solutions with 's PROM circuit technology for use in mobile, IOT, client, network, and server segments. Job responsibilities include R

Sr. RTL/Digital Design Engineer

Xpeerant Incorporated

Remote

Contract

Xpeerant prides itself in assisting our customers to achieve Market Window success by identifying and placing critical resource requirements. Securing the right talent is the most critical component of any project and directly relates to the success of any business. Market opportunities wait for no one. Finding the ideal fit is what Xpeerant has done for the last 26 years! We have RTL Design Engineer opportunities! If you meet the following description, let us hear from you! The ideal candidate

ASIC RTL Verification Engineer

Technical Link

Remote

Contract

Job Title: ASIC RTL Verification Engineer Location: Remote Duration: 1 Year (LOA) We are seeking skilled ASIC RTL Verification Engineers to join our dynamic team. The ideal candidates will have expertise in ASIC-based RTL verification, with a strong understanding of UVM methodology. Experience with Serdes, High Bandwidth Memory (HBM), and DDR4/5 is essential for success in this role. Key Responsibilities: Conducting ASIC-based RTL verification using industry-standard methodologies. Developing an

RTL Design Engineer

Xoriant Corporation

Hybrid in San Jose, California, USA

Contract

Title: RTL Engineer Location: San Jose, CA | San Diego, CA | Austin Texas Duration: 6+ months (Possible Extension-Long Term Project) Job Description As a senior RTL design engineer, you will work as part of a memory controller IP design team.You will be tasked with driving the RTL design, performance and power optimization of various sub-blocks of the dynamic memory controller.Solid engineer foundation and RTL design experience is desired for success.Key responsibilities include: Produce quality

CPU RTL Power Engineer

Qualcomm Technologies

On-site in Austin, Texas, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for CPU RTL Power targeted for high performance, low power devices. In this role, you will be responsible for all key aspects of CPU power modeling and analysis, and RTL power estimation and optimization of high-performance energy efficient CPU designs. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, C

Senior Physical Design Engineer

SambaNova Systems

On-site in Palo Alto, California, USA

Full-time

Working at SambaNova This role presents a unique opportunity to shape the future of AI and the value it can unlock across every aspect of an organization's business and operations. SambaNova is hiring a Senior Physical Design Engineer who will be responsible for developing and maintaining synthesis and physical composition flow utilizing leading industry tools. In this role, you will play a unique and critical role in the development of the SambaNova DataScale system and you will be provided wi

RTL ASICS Engineer

Qualcomm Technologies

On-site in Boxborough, Massachusetts, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: At Qualcomm, we believe in the power of technology. For decades, our innovations have transformed entire industries, improved billions of lives, and addressed many of society's biggest challenges. With the world becoming increasingly connected, we have a tremendous opportunity to shape a better future. As an R&D engine that has revolutionized the way people connect, our a

Senior Silicon Design Engineer - Onsite

VIVA USA INC

On-site in Santa Clara, California, USA

Contract

Title: Senior Silicon Design Engineer Description: THE ROLE: This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification THE PERSON: Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams RESPONSIBILTIES: This engineer will work on high-speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and

System Cache Architect and Design Engineer

Qualcomm Technologies

On-site in San Diego, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: The SoC memory team group consists of a multi-disciplinary group involved from early product specification and analysis effort to final RTL delivery of high-performance memory systems to the SoCs. A key function of the job is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis feedback. Candidates should have strong

CPU Physical Design Engineer - Austin, TX

Qualcomm Technologies

On-site in Austin, Texas, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a CPU Physical Design Engineer, you will work with microarchitecture and RTL design team to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows. Roles and Responsibilities Work with CPU microarchitecture team to understand specifications and design trade offs in pipeline and structure sizing.Perform feasibilities to

ASIC Design Engineer

Jobot

On-site in San Jose, California, USA

Full-time

This Jobot Job is hosted by: Maria Reyes Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $120,000 - $150,000 per year A bit about us: Join our dynamic team! We are a leading innovator in HD video technology. Since 2014 we revolutionized the video surveillance market with the introduction of HD-TVI (High Definition Transport Video Interface). Our groundbreaking technology has earned widespread acclaim, becoming the preferred choice for tier

Senior ASIC Design Engineer

Jobot

On-site in San Jose, California, USA

Full-time

This Jobot Job is hosted by: Maria Reyes Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $140,000 - $220,000 per year A bit about us: Join our dynamic team! We are a leading innovator in HD video technology. Since 2014 we revolutionized the video surveillance market with the introduction of HD-TVI (High Definition Transport Video Interface). Our groundbreaking technology has earned widespread acclaim, becoming the preferred choice for tier

Hardware Design Engineer

Themesoft Inc

On-site in Mountain View, California, USA

Full-time, Part-time, Contract, Third Party

Location : HYBRID, Mountain View, California Skills Required: Years of Experience Required: 10+ overall years of experience in the field. Degrees or certifications required: Looking for actual experience degree is less important, however a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree would be relevant. Disqualifiers: Candidates with history of short-term contracts / job hopping will not be eligible for the role. Best vs. Average: The idea

Physical Design Engineer - Onsite

Experis

On-site in Phoenix, Arizona, USA

Full-time

L3 (7-15 yrs.) or L4(15+ yrs.)) ONSITE SOC Integration/STA/Synthesis Engineer Required Skills: Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, constraints, static timing analysis, formal verification, Gate level functional & timing ECO in advanced technology nodes Develop & document STA & Synthesis strategies. Interact with methodology teams to address challenges related to new technology node