RTL design Jobs

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Senior ASIC Design Engineer

Marici Solutions

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San Jose, California, USA

Contract

Position: Senior ASIC Design Engineer Emulation(HAPS Engineer) Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-lev
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Posted 2 days ago

Design Verification Engineer

AppLab Systems Inc

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No location provided

Full-time, Contract

Position : Design Verification Engineer Location: Sunnyvale CA /Redmond WA/ Austin TX/Remote Duration: Full Time Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close func
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Posted 5 days ago | Updated 11 hours ago

Design Verification Engineer

Mirafra Inc

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San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot
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Posted 31 days ago | Updated 14 days ago

Design Verification Engineer (GPU)

BayOne Solutions

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San Jose, California, USA

Contract

Job Title - Design Verification Engineer (GPU) Duration 9 + Month (With the possibility of extension) Location:- San Jose (Onsite) Pay Rate :- $100/hr. - 120/hr. on w2 Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including th
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Posted 16 hours ago | Updated 15 hours ago

DFT/DFX Engineer

Mirafra Inc

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Austin, Texas, USA

Full-time

Experience with Scan Shift Network is required. Experience with Tessent is highly desired. Good exposure to scripting with Tcl/Perl Responsibilities: Steer the Automation for SSN enablement Understand SOC requirements and project milestones to help define a DFT architecture which optimally balances between coverage, test-time, and execution. Create a detailed implementation spec which documents details of the architecture including SOC-level interface, clock design, and support of various test/d
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Posted 60+ days ago | Updated 14 days ago

Design for Test Engineer (DFT)

Yoh - A Day & Zimmerman Company

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Remote or Austin, Texas, USA

Full-time

Design for Test Engineer (DFT) The role is Design for Test (DFT) for high-performance designs going into industry AI/ML architectures. This will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage & facilitating debug and yield learnings while minimizing design intrusions. Scope: Implementation of DFT features into RTL (using Verilog). Understand DFT Architectures & micro-archit
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Posted 3 days ago | Updated 2 days ago

FPGA Engineer III

Dexian DISYS

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Queen Creek, Arizona, USA

Contract

Job Description: Duration: 4+ Months Job Title :: FPGA Engineer Location : Mesa, AZ :: 100% Onsite Rate Range : $60-$63/hr Job Description: As an FPGA Engineer, you will have the following responsibilities: Architect, design, implement, and validate FPGA RTL to enable prototype systems that drive display subsystem. Collaborate with cross-functional teams to define RTL specs and plan feature development roadmaps Work closely with software team to write low-level drivers that interface with RTL.
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Posted 17 days ago | Updated 1 hour ago

Design for Test Engineer (DFT)

Yoh - A Day & Zimmerman Company

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Remote or Austin, Texas, USA

Full-time

Design for Test Engineer (DFT) The role is Design for Test (DFT) for high-performance designs going into industry AI/ML architectures. This will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage & facilitating debug and yield learnings while minimizing design intrusions. Scope: Implementation of DFT features into RTL (using Verilog). Understand DFT Architectures & micro-archit
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Posted 28 days ago | Updated 2 hours ago

Sr. Staff Post Silicon Validation Engineer - Direct hire/Full time (Onsite)

Maxonic, Inc.

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Austin, Texas, USA

Full-time

Maxonic maintains a close and long-term relationship with our direct client. In support of their needs, we are looking for a Sr. Staff Post Silicon Validation Engineer Job Description: Job Title: Sr. Staff Post Silicon Validation Engineer Job Type: Fulltime Job Location: Austin, TX or Palo Alto, CA Work Schedule: Onsite 5 days a week The candidate will focus on developing Post-Silicon validation plan, debug tools, and infrastructure for a custom SoCs and Platform designs for Autopilot and AI. As
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Posted 13 days ago

FPGA Design Engineer

GlobalLogic Inc.

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Warren, New Jersey, USA

Third Party, Contract

Job Description: You will innovate in 4G, 5G, and O-RAN systems in a competitive atmosphere.Experience in FPGA design and development.Proficiency in Verilog/SystemVerilog for digital logic design.Experience with FPGA development tools such as Xilinx Vivado, and Intel Quartus.Knowledge of wireless communication systems, 4G/5G networks, and O-RAN architectures.Strong understanding of DSP algorithms and their FPGA implementations.Experience in debugging in the lab using Vivado ILAs and experience
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Posted 60+ days ago | Updated 12 days ago

Sr ASIC/FPGA VHDL Design Engineer Secret Clearance Required No Sponsorship Available

ZoeTech Staffing LLC

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Camden, New Jersey, USA

Full-time

Schedule: 9/80 Regular with every other Friday off Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols. The company has state-of-the-art EDA flows/
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Posted 33 days ago | Updated 15 hours ago

Design Verification Engineer

Innova Solutions, Inc

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Remote or Mountain View, California, USA

Third Party, Contract

A client of Innova Solutions is looking for an Design Verification Engineer. Position type: Contract Duration: 12+ Months Location: Mountain View, CA (Onsite Job) As a Design Verification Engineer, you will need: Minimum Qualifications: Experience in SV and UVM and good debugging skills.Understanding of AMBA protocols.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional
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Posted 40 days ago | Updated 4 days ago

High-Level AI Platform API Developer Sr. Software Engineer to work with a company a t the forefront of hardware technologies accelerating and optimizing FHE encryption via Artificial Intelligence.

VortexLink

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Campbell, California, USA

Full-time

High-Level AI Platform API Developer Sr. Software Engineer Fulltime opportunity in Campbell, CA(Hybrid) As a senior member of the System Software team, you will play a key role in crafting and evolving C/C++ APIs that enable AI/ML developers to program our ASIC fabric efficiently. You will also collaborate closely with the RTL team to understand the hardware architecture and develop functional tests for the ASIC. Our ASIC, a PCIe-based device with dataflow computational and memory resources, req
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Posted 60+ days ago | Updated 9 days ago

Design Verification Engineer

Yoh - A Day & Zimmerman Company

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Remote or Santa Clara, California, USA

Full-time

Design Verification Engineer Scope: Design and development of the IO subsystems for a high-performance SoC from scratch, working closely with the Architecture and RTL teams. Develop detailed block-level design specifications and plans for a high-performance IO Subsystem. Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers. Develop and optimize the IO subsystem design to ensure functionality and performance are in a
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Posted 60+ days ago | Updated 2 days ago

Design Verification Engineer

Yoh - A Day & Zimmerman Company

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Remote or Santa Clara, California, USA

Full-time

Design Verification Engineer Scope: Design and development of the IO subsystems for a high-performance SoC from scratch, working closely with the Architecture and RTL teams. Develop detailed block-level design specifications and plans for a high-performance IO Subsystem. Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers. Develop and optimize the IO subsystem design to ensure functionality and performance are in a
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Posted 60+ days ago | Updated 2 hours ago

Design Verification Engineer

JConnect Inc

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San Jose, California, USA

Full-time

Role: Design Verification Engineers (SoC-5, PCIe-5)Location: Bay AreaSalary: 160-240k (DOE) Free health insurancePTOs: 10 Business days (Including sick leaves) Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium) Job Description: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from speci
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Posted 60+ days ago | Updated 19 hours ago