RTL design Jobs

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Senior RTL Analysis Methodology Engineer

NVIDIA Corporation

Santa Clara, California, USA

Full-time

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

FPGA Design Engineer

KLA

Ann Arbor, Michigan, USA

Full-time

Company Overview KLA is a global leader in diversified electronics for the semiconductor manufacturing ecosystem. Virtually every electronic device in the world is produced using our technologies. No laptop, smartphone, wearable device, voice-controlled gadget, flexible screen, VR device or smart car would have made it into your hands without us. KLA invents systems and solutions for the manufacturing of wafers and reticles, integrated circuits, packaging, printed circuit boards and flat panel d

ASIC Engineering Technical Leader (Design)

Cisco Systems, Inc.

San Jose, California, USA

Full-time

The application window is expected to close on 8/30/25. This role will be based onsite out of our San Jose, CA office. The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture

SDC Engineer

eInfochips Inc

San Jose, California, USA

Full-time

Position: SDC Engineer (eInfochips Inc) Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop effi

Senior Electrical Engineer (FPGA Design)

Harris Corporation

Camden, New Jersey, USA

Full-time

L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers' mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do. L3Harris Technologie

Design Verification Engineer

Xoriant Corporation

Austin, Texas, USA

Contract

Job Title: Design Verification Engineer #368877 Duration: 12+ months (Possible Extension-Long Term Project) Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite) Description As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updatesDebug functional errors in RTL model using simulation and debug tools.Maintain efficient and clean re

Senior Synthesis Flow CAD Engineer

NVIDIA Corporation

Santa Clara, California, USA

Full-time

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify huma

Clock Distribution Engineer, Dojo

Tesla Motors

Palo Alto, California, USA

Full-time

The Dojo Hardware team is looking for a Clock Distribution Engineer to work in Palo Alto, CA. This Engineer will be responsible for the design and implementation of clocks at both the SOC and IP level. Responsibilities Design custom clock distribution from PLL to sub-blocks meeting low latency and jitter specs for various SOC clocks Write modular clock RTL to handle changes, integrating it into designStrong tcl knowledge to automate the clock tree generation based on bottoms-up load feedbackWor

STAEngineer

Cloudious

San Jose, California, USA

Contract

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficien

Senior ASIC Timing Engineer

NVIDIA Corporation

Westford, Massachusetts, USA

Full-time

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify huma

Senior ASIC Verification Engineer - HSIO

NVIDIA Corporation

Westford, Massachusetts, USA

Full-time

NVIDIA is seeking a highly motivated Senior Design Verification Engineer to play a critical role in verifying next-generation NVLink High-Speed I/O (HSIO) controllers for industry-leading GPUs. This is a unique opportunity to contribute to cutting-edge products spanning consumer graphics, self-driving vehicles, and artificial intelligence-all within a collaborative, technology-driven environment. At NVIDIA, we're redefining the future of computing. From revolutionizing gaming and cinematic visua

Senior ASIC Front End Infrastructure Engineer

NVIDIA Corporation

Remote or Santa Clara, California, USA

Full-time

NVIDIA is seeking elite ASIC RTL/Verification ASIC engineers to develop the core Verification and RTL infrastructure of the world's leading GPUs. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to artificial intelligence to self-driving cars and supercomputers. Our team of dedicated Infrastructure engineers continuously upgrades the NVIDIA Hardware design environment. We focus relentlessly

Senior ASIC Design Engineer- Emulation (HAPS Engineer)

Cloudious

San Jose, California, USA

Contract

Position: Senior ASIC Design Engineer- Emulation (HAPS Engineer) Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top

Senior GPU Low Power Architect

NVIDIA Corporation

Santa Clara, California, USA

Full-time

We are looking for a Senior GPU Low Power Architect within our Hardware Team! NVIDIA is known as a world leader in providing energy-efficient high-performance products, and we continue to invest in the research and development of hyper-efficient GPU and SOC architectures that power AI, Automotive, Graphics, and Mobile products. Widely considered to be one of the technology world's most desirable employers, you will interact with world class engineers on the cutting edge of emerging GPU and AI te

Hardware Security, Lead Engineer

Oracle Corporation

Santa Clara, California, USA

Full-time

Job Description Department Description As part of the Oracle Hardware Development (OHD) Hardware Engineering Organization, you will be involved in developing the next generation of Oracle hardware that underlies all of Oracle's Cloud and Enterprise platform offerings. These systems utilize leading edge technology to deliver record-breaking performance, simplified management, security, self-monitoring and diagnosis as well as cost-saving efficiencies. You will apply your expertise in detailed s

Design verification Engineer

Innova Solutions, Inc

Mountain View, California, USA

Contract, Third Party

A client of Innova Solutions is immediately hiring a Design verification Engineer Position type: Contract Duration: Contract Location: Mountain View, CA (Hybrid) As a Design verification Engineer, you will need: Must-Have Skills: 9+ years of experience as Design Verification EngineerStrong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-

Emulation Engineer

eInfochips Inc

San Jose, California, USA

Full-time, Third Party

Job Description:What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.Option to engage in block-level RTL design or block or top-level IP integration.Collaborate with Software, Design, and Verification teams to validate the functional and performance obj

Emulation Engineer at San Jose CA

Mirafra Inc

San Jose, California, USA

Full-time

Job Description: Develop state-of-the-art emulation environments that will be used to evaluate the performance and functionality of multi-terabit systems.Developing emulation infrastructure using C/C++ and TCLAs a team member, work closely with the design, DV, power, and post-silicon diagnostic teams.Assist with test plan design, test implementation, and debugging during the pre-silicon emulation process.Develop tests to generate complex traffic, and performance scenarios to catch potential post

FPGA Engineer

OSI Engineering, Inc.

Sunnyvale, California, USA

Contract

A globally leading technology company is looking for an experienced FPGA Engineer to architect, design, and validate RTL for advanced display subsystem prototypes. In this role, you will collaborate with cross-functional teams, contribute to hardware bring-up, and support low-level software integration. Strong skills in digital interface debugging, FPGA tools, and C/C++ firmware development are essential. If you're passionate about innovation and display technology, we invite you to apply! Job

DV Engineers DDR (either IP or SoC level experience)- Remote

E-Solutions, Inc.

California, USA

Full-time, Contract, Third Party

Role: DV Engineers DDR (either IP or SoC level experience) Work Location: USA (Remote) Experience: 10+ Years Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own f