RTL design Jobs

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RTL design Engineer

Mirafra Inc

San Jose, California, USA

Full-time

Job Description: Strong Logic Design, RTL coding (Verilog HDL) and debugging skills Analyze and resolve Lint, CDC and RDC issues in the design Understanding of low power design and validation techniques including UPF Experience with constraint generation, timing closure analysis, formal verification, low power checks using UPF flows and ECO implementation. Experience with writing assertions and doing negative checks to validate assertions Experience with Silicon validation/Bring-up Experience w

RTL Design Engineer

Triple Crown Consulting

Dallas, Texas, USA

Contract

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth. Contract Position Duration: 6+ Months Location: Dallas, Texas We are seeking a Senior ASIC RTL Design Engineer with strong IP integration experience and/or a Functional Safety En

RTL/ASIC Design Engineer

LanceSoft Inc.

Dallas, Texas, USA

Contract

We are seeking RTL/ASIC Design Engineer to join our team In this hands-on role, you will be responsible for RTL Coding and CDC, Lint using various tools and equipment in a fast-paced production environment. Responsibilities: 6+ years of experience in RTL - IP design (preferred) and/or SoC integration.Hands on experience in RTL codding.Experienced in QC tools Lint, CDC etc.Experience on PCIE, MIPS, UFS and SerDesExperience on IP integrationMust have experience in doing FMA/FMEDA for IP RTL module

ASIC/RTL Design Engineer - Senior at San Jose, CA

Infobahn Softworld Inc.

Santa Clara, California, USA

Third Party, Contract

TOP 3 SKILLS: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have KEY RESPONSIBILITIES: Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements. Collaborate with architecture and hardware teams to understand the requirements. Work with verification and p

Design Verification Engineer

Veear

Sunnyvale, California, USA

Full-time

Requirements: Thorough knowledge of microprocessor or SOC design with 2+ years of direct work experience in one or more of the following areas:High performance cache controllers - pipeline design, hazard detection, parity/ECC generation, coherency policies, replacement policiesCoherent on-chip Fabrics for high performance SOCs and design of associated control structuresKnowledge of SystemVerilogExperience with simulators and waveform debugging toolsKnowledge of logic design principles along with

RTL Engineer

Cloudious

Santa Clara, California, USA

Contract

Title: RTL Engineer Location: Santa Clara, CA (Day-1 onsite) Duration: 6 Months Role: Integrate RISC-V Core to SoC Key Responsibilities Integrate RISC-V CPU cores into SoC designs, collaborating with cross-functional teams (DV, physical design, architecture, verification, and post-silicon validation) to ensure seamless delivery. Develop and optimize RTL (using Verilog/SystemVerilog) for core, interconnect, and memory subsystems. Evaluate and integrate third-party IP, ensuring performance, power,

Senior Physical Designer

Triple Crown Consulting

Irvine, California, USA

Contract

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth. CONTRACT Position: 6-12 Months Location: Onsite in Irvine, CA We are looking for a highly skilled Senior SoC/ASIC Physical Design Engineer to lead and drive all aspects of physic

Digital Design Engineer

SPECTRAFORCE TECHNOLOGIES Inc.

Redmond, Washington, USA

Contract

Job Title: Silicon DD Engineer IV Duration: 12 Months Location: Redmond, WA or Sunnyvale, CA Role: Develop and test RTL modules on AMD/Xilinx FPGA devices (required) and ASIC targets (preferred) Develop and maintain build/simulation scripts Write test cases using Python to validate our design Create software interfaces from our FPGA-based systems to Windows and Linux systems software at the HAL layer Collaborate in a team environment across multiple engineering disciplines and with researchers M

RTL Engineer || Dallas ,TX(Onsite)

Zodiac Solutions Inc.

Texas, USA

Part-time, Contract, Third Party

Title: RTL Engineer Location: Dallas ,TX(Onsite) Job Description : Understand customer's requirements /specifications /tender enquiry. Define DSP, System and Board architecture. Project ownership from concept to delivery. This includes identifying risks, dependencies, creating mitigation plan, tracking project schedule, discussions with customers, design reviews. Partition the algorithms for implementing in FPGA and/or in SW. Identify the building blocks & Signal Processing functions. Provide e

Digital Design Engineer

SGS Consulting

Remote

Contract

SENIOR DIGITAL DESIGN ENGINEER 100% REMOTE - Within USA About the Role: What are the top non-negotiable skill sets required for this role? Experience in RTL coding, synthesis, and/or SoC IntegrationExperience in digital design ArchitectureFamiliarity with Verilog, System Verilog coding Duties: Contribute to the development of efficient Architectures and contribute to ASIC digital Architecture, design and verificationIPs integrationUnderstand Design for Verification conceptsDrive the top-level

Principal Digital Design Engineer

OSI Engineering, Inc.

San Jose, California, USA

Full-time

Principal Digital Design Engineer A premier chip and silicon IP provider focused on accelerating and securing data is seeking an exceptional Principal Digital Design Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This is an exciting opportunity to work alongside some of the industry s most innovative engineers on cutting-edge technology that drives faster and more secure data solutions. In this full-time role, the Principal Digital Design Engineer will report directly to

Senior ASIC Engineer, Static Timing Analysis

Infoyogi LLC

San Jose, California, USA

Contract

Senior ASIC Engineer, Static Timing Analysis -AMDJP00004058 Location: San Jose, CA- Onsite. Alternate location: Colorado office - 3100 Logic Dr, Longmont Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff & the expertise we need with these tools (DC/PT). Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA tool compe

CPU Implementation Engineer

Apple, Inc.

No location provided

Full-time

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to ou

Synthesis & Low power Design

Mirafra Inc

Mountain View, California, USA

Full-time

Own and optimize RTL-to-GDSII implementation flows using Synopsys Fusion Compiler, including synthesis, placement, routing, and signoff.Develop and maintain RTLA-based power estimation and optimization flows, integrating with PrimePower RTL and design environments.Collaborate with RTL and physical design teams to define timing constraints, UPF-based power intent, and switching activity annotations for accurate power analysis.Drive methodology improvements for early RTL power estimation, scenario

DFT Engineer

Canvendor Inc

Austin, Texas, USA

Contract, Third Party

Position: DFT Engineer Location: Austin, TX (Onsite) Type: Contract Responsibilities: Responsible for developing, maintaining and supporting flows across all company business units and projects Architecting methodologies and flows for an integrated, RTL centric "shift left" DFT environment across company IPs, ASICs and SoC designs.Writing and automating RTL for advanced DFT and DFD features not currently supported by the EDA vendorsDeveloping automated verification test bench and sequence creati

Senior Hardware Design & Validation Engineer

Experis

Austin, Texas, USA

Full-time

Our client, a leader in cutting-edge technology, is seeking a Senior Hardware Design & Validation Engineer to join their team. As a Senior Hardware Design & Validation Engineer, you will be part of a dynamic engineering team supporting innovative projects in AI and mixed-signal chip technologies. The ideal candidate will have strong analytical skills, a collaborative mindset, and a passion for technology, which will align successfully in the organization. Job Title: Senior Hardware Design & Vali

Senior ASIC Clock Engineer

NVIDIA Corporation

Remote or Santa Clara, California, USA

Full-time

NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on pe

ASIC Design Engineer

Jobot

Atlanta, Georgia, USA

Full-time

Leading semiconductor manufacturer with competitive compensation, generous bonus, and stock options! Also offering relocation bonus and/or be willing to relocate to Atlanta, GA This Jobot Job is hosted by: Michael Ramsey Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $125,000 - $200,000 per year A bit about us: Leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center mark

RTL Engineer: Integrate RISC-V Core to SoC

Intelliswift Software Inc

Santa Clara, California, USA

Contract

Job Title: RTL Engineer: Integrate RISC-V Core to SoC Location(s): Santa Clara, CA - Onsite Must Have skills: 5+ years of experience in RTL design, SoC integration, or related areas.Strong hands-on experience with hardware description languages (Verilog, SystemVerilog, VHDL), EDA tools, and simulators (VCS, NC, Verilator).Deep understanding of SoC design, integration, and high-performance interfaces (e.g., AXI, TileLink, PCIe, Ethernet).Proven ability to debug and optimize designs for functiona

GPU Formal Design Verification

West Coast Consulting LLC

California, USA

Contract

Job Description ONSITE in San Jose, CA or Austin, TX Vertical Technical Description As a Contract - Formal Design Verification Engineer, you will be responsible for developing formal constraints, checks, and cover properties to new and existing design blocks towards verifying sequential equivalence for clock gating logic & so, verifying design features using assertions and verifying datapath equivalence of C and RTL models. You will diagnose formal failures and work closely with RTL designers t