Job Description
ONSITE in San Jose, CA or Austin, TX
Vertical Technical
Description
As a Contract - Formal Design Verification Engineer, you will be responsible for developing formal constraints, checks, and cover properties to new and existing design blocks towards verifying sequential equivalence for clock gating logic & so, verifying design features using assertions and verifying datapath equivalence of C and RTL models. You will diagnose formal failures and work closely with RTL designers to update formal setup or RTL code. GPU designs provide a wealth of technical challenges in memory hierarchy, parallel processing units, and complex mathematical units. This is a challenging and rewarding position where you will learn cutting-edge design and verification techniques from an exceptionally talented team, and where your contributions will make a visible impact to the end product.
Develop formal verification setup using System Verilog modules and Assertions
Run formal verification checks, analyze the results, and debug any issues.
Develop and enhance constraints, checks, and cover points to achieve verification quality.
Verify GPU design blocks using formal verification approaches like sequential equivalence checking, property-based feature verification and datapath verification using C models.
Hands-on experience in developing formal based datapath verification setups using RTL & C Models
Hands-on experience in developing formal property-based feature verification setups
In-depth expertise on proof depth and convergence analysis for formal setups
Root cause formal failures to identify design or test setup issues.
Analyze and deploy formal convergence techniques like abstraction, blackboxing and design reductions.
Work closely with cross-functional teams, including design, architecture, and software teams, to ensure that verification efforts are aligned with project goals and requirements.
Participate in the development and improvement of verification methodologies, tools, and flows to increase efficiency and effectiveness of verification efforts.
Adhere to project execution and planning approaches using Confluence, JIRA and relevant techniques.
Create and maintain documentation for formal verification test plans, convergence reports, complexity analysis reports and results.
Responsible in driving formal verification tasks & report to project verification leads as required
Requirements
BSEE, Computer Engineering, or Computer Science bachelor's degree and a minimum of 3+ years of experience o Masters or Ph.D. degree preferred
Good understanding of CPU and/or GPU design architecture
Strong experience or exposure to System Verilog (SV) and System Verilog Assertion (SVA) coding skills is required
Experience in developing formal verification setups is a must
Experience in developing constrained random testbenches is preferred
Experience with formal verification tools such as VC Formal, Jasper Gold, or Questa Formal
Experience working in a Linux environment
Excellent communication skills and be able to work with cross-functional teams to execute verification plan
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: wesca004
- Position Id: JOB-5698
- Posted 30+ days ago
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