asic Jobs

21 - 40 of 12,399 Jobs

ASIC/FPGA Research Engineer - Digital DesignJob Title - ASIC/FPGA Research Engineer - Digital Design

University of Southern CaliforniaCompany Name - University of Southern California

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Arlington, Virginia, USA

Full-time

USC's Information Sciences Institute (ISI), a unit of the university's Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications and artificial intelligence technologies. ISI's 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Arlington, VA; Marina Del Rey, CA; and Waltham, MA. Perform digital hardware design in a fast-movin

Sr Principal ASIC FPGA EngineerJob Title - Sr Principal ASIC FPGA Engineer

GENERAL DYNAMICS MISSION SYSTEMSCompany Name - GENERAL DYNAMICS MISSION SYSTEMS

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Scottsdale, Arizona, USA

Full-time

Basic Qualifications Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience. CLEARANCE REQUIREMENTS: Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject

FPGA/ASIC Design SpecialistJob Title - FPGA/ASIC Design Specialist

Rolls RoyceCompany Name - Rolls Royce

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Indianapolis, Indiana, USA

Full-time

Job Description Job Title: FPGA/ASIC Design Specialist Working Pattern: Full-time Working location: Indianapolis, IN Rolls-Royce is looking for a FPGA/ASIC (Field Programmable Gate Arrays / Application Specific Integrated Circuit) Design Specialist to join our growing team. This is an exciting opportunity to work on flagship Rolls-Royce programs and play a vital role in solving some of the most complex and interesting technological challenges in the industry while being part of a global, mu

Senior ASIC Verification EngineerJob Title - Senior ASIC Verification Engineer

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Austin, Texas, USA

Full-time

The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Verification Engineer interested in innovative approaches to drive design quality in our IP. This position offers the opportunity to impact an array of products while collaborating with teams from design, architecture, verification, and integration. You should have real passion for innovation, methodology and automated solutions that drive product quality. What you'll be doing: Develop test plans, tests and verification infrastruct

Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASICJob Title - Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASIC

Motion Recruitment Partners, LLCCompany Name - Motion Recruitment Partners, LLC

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Irvine, California, USA

Full-time

Our client is a glbal infrastructure technology leader built on more than 60 years of innovation within the semiconndutor and Manufacturing space for communications. They are urgently seeking a Sr. level Digital Signal Processing (DSP) R&D Engineer to join their growing team. Responsibilities include: Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation Develop and

Staff ASIC & FPGA Design Engineer (HYBRID TELEWORK)Job Title - Staff ASIC & FPGA Design Engineer (HYBRID TELEWORK)

Lockheed MartinCompany Name - Lockheed Martin

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King of Prussia, Pennsylvania, USA

Full-time

Job ID: 683774BR Date posted: Apr. 07, 2025 Description:We are committed to work-life balance by promoting this hybrid telework opportunity. These job requirements allow the employee to work at a Lockheed Martin-designated office or job site for part of their schedule and has a predefined regular, recurring telework schedule for the remaining part of their work schedule. Who We Are Lockheed Martin is dedicated to shaping, developing, & advancing technologies & capabilities with a focus on our

Staff ASIC & FPGA Design Engineer (HYBRID TELEWORK)Job Title - Staff ASIC & FPGA Design Engineer (HYBRID TELEWORK)

Lockheed MartinCompany Name - Lockheed Martin

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King of Prussia, Pennsylvania, USA

Full-time

Staff ASIC & FPGA Design Engineer (HYBRID TELEWORK)Job Title - Staff ASIC & FPGA Design Engineer (HYBRID TELEWORK)

Lockheed MartinCompany Name - Lockheed Martin

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King of Prussia, Pennsylvania, USA

Full-time

ASIC EngineerJob Title - ASIC Engineer

AdientOne LLCCompany Name - AdientOne LLC

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California, USA

Contract

Role: ASIC Engineer Location: Clara CA 95054 OR Longmont CO 80503 Duration: 12+months Job Description: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scrip

ASIC STA & CAD EngineeringJob Title - ASIC STA & CAD Engineering

Coretek LabsCompany Name - Coretek Labs

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Longmont, Colorado, USA

Full-time, Contract, Third Party

Job Title: ASIC STA & CAD Engineering Location: Longmont, Colorado (Hybrid) Duration: Long Term Contract Rate: $50-60/hr. Domain: Engineering Key Responsibilities: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Engaging closely with block and SoC design teams to under

ASIC Timing EngineerJob Title - ASIC Timing Engineer

SmksoftCompany Name - Smksoft

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San Jose, California, USA

Contract

Job Title: Chip-Level Timing Constraint Development EngineerLocation: San Jose, CA - You must be already located in the San Jose area. Duration: 12+ MonthsVisa: Open (No restrictions) Responsibilities: 5 years of experience Define, develop, and validate timing constraints (SDC) for complex chip-level ASIC designs Perform static timing analysis (STA) to ensure full timing coverage and closure Collaborate with RTL, architecture, and physical design teams on clock structures and design intent Opti

ASIC Engineer, ImplementationJob Title - ASIC Engineer, Implementation

Meta Platforms, Inc. (f/k/a Facebook, Inc.)Company Name - Meta Platforms, Inc. (f/k/a Facebook, Inc.)

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Sunnyvale, California, USA

Full-time

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following positions in Sunnyvale, CA ASIC Engineer, Implementation: Run logic/physical synthesis using advanced optimization techniques and generate optimized gate level netlist for Timing, Area, and Power. (ref. code REQ-2503-148357: $141,682/year - $154,000/year). Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus

ASIC Design EngineerJob Title - ASIC Design Engineer

Yochana IT SolutionsCompany Name - Yochana IT Solutions

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Santa Clara, California, USA

Contract, Third Party

ASIC Design Engineer Location: Santa Clara, CA Onsite Contract Overview of the Role As an ASIC Design Engineer , you will play a crucial role in the development and optimization of our cutting-edge ASIC solutions. Your work will directly impact the efficiency, performance, and scalability of our products, driving forward the company's objectives and contributing to technological innovations that shape the industry. Detailed Responsibilities Run and manage Fusion Compiler, ICC II, and Innovus

Lead ASIC & FPGA Design Engineer - Vitis HLS (HYBRID TELEWORK)Job Title - Lead ASIC & FPGA Design Engineer - Vitis HLS (HYBRID TELEWORK)

Lockheed MartinCompany Name - Lockheed Martin

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Norristown, Pennsylvania, USA

Full-time

Job ID: 683766BR Date posted: Apr. 07, 2025 Description:We are committed to work-life balance by promoting this hybrid telework opportunity. These job requirements allow the employee to work at a Lockheed Martin-designated office or job site for part of their schedule and has a predefined regular, recurring telework schedule for the remaining part of their work schedule. Who We Are Lockheed Martin is dedicated to shaping, developing, & advancing technologies & capabilities with a focus on our

ASIC & FPGA EngineerJob Title - ASIC & FPGA Engineer

Sun Technologies,Inc.Company Name - Sun Technologies,Inc.

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Remote

Contract

Job Title: ASIC & FPGA Engineer Duration: up to 12 months contract (with the possibility of extension) Location: Remote Work / Work from Home Pay Range: $85 - $90/hr on W2 Featured Benefits: Medical Insurance in compliance with the ACA401(k)Sick leave in compliance with applicable state, federal, and local laws Job Description: Responsible for ASIC & FPGA developmentExperience in developing, testing, and integrating FPGA platformsCollaboration with Software Engineers and other ASIC/FPGA engine

Lead ASIC & FPGA Design Engineer - Vitis HLS (HYBRID TELEWORK)Job Title - Lead ASIC & FPGA Design Engineer - Vitis HLS (HYBRID TELEWORK)

Lockheed MartinCompany Name - Lockheed Martin

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King of Prussia, Pennsylvania, USA

Full-time

Lead ASIC & FPGA Design Engineer - Vitis HLS (HYBRID TELEWORK)Job Title - Lead ASIC & FPGA Design Engineer - Vitis HLS (HYBRID TELEWORK)

Lockheed MartinCompany Name - Lockheed Martin

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King of Prussia, Pennsylvania, USA

Full-time

Sr ASIC/FPGA VHDL Design Engineer Secret Clearance Required No Sponsorship AvailableJob Title - Sr ASIC/FPGA VHDL Design Engineer Secret Clearance Required No Sponsorship Available

ZoeTech Staffing LLCCompany Name - ZoeTech Staffing LLC

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Camden, New Jersey, USA

Full-time

Schedule: 9/80 Regular with every other Friday off Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols. The company has state-of-the-art EDA flows/

ASIC / FPGA EngineerJob Title - ASIC / FPGA Engineer

ApolisCompany Name - Apolis

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Cedar Rapids, Iowa, USA

Full-time, Contract

Job Title: ASIC / FPGA Engineer Location: Cedar Rapids, IA (5 days onsite) Contract: 12+ Months Experience range - 6-15 years* Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow * Contribute to engineering estimates for new program pursuits. * May provide technical leadership for project design teams by breaking down

ASIC Engineer (Design Verification)Job Title - ASIC Engineer (Design Verification)

CloudiousCompany Name - Cloudious

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Sunnyvale, California, USA

Third Party, Contract

ASIC Engineer (Design Verification) Bay Area, CA or Austin, TX 12 Months Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collab