asic Jobs

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Principal Digital ASIC Design EngineerJob Title - Principal Digital ASIC Design Engineer

91140551Company Name - 91140551

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Clearfield, Utah, USA

Full-time

Job Title: Principal Digital ASIC Design Engineer Location: Clearfield, UT Job Type: Direct-Hire Position Job Description: We are seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. As a Principal Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies.You will be responsible for implementing designs from RTL through synthesis.You will work in multi-disciplinary teams wi

Sr Director, ASIC EngineeringJob Title - Sr Director, ASIC Engineering

PaloAlto NetworksCompany Name - PaloAlto Networks

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Santa Clara, California, USA

Full-time

Company Description Our Mission At Palo Alto Networks everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we're looking for innovators who are as committed to shaping the future of cybersecurity as we are. Who We Are We take our mission of

ASIC Engineer, Design VerificationJob Title - ASIC Engineer, Design Verification

Meta Platforms, Inc. (f/k/a Facebook, Inc.) Company Name - Meta Platforms, Inc. (f/k/a Facebook, Inc.)

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Sunnyvale, California, USA

Full-time

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following positions in Sunnyvale, CA ASIC Engineer, Design Verification: Evaluate, develop and drive next generation technologies. (ref. code REQ-2505-150926: $229,066/year to $234,520/year). Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus or equity or sales incentives, if applicable. In addition to base salary, M

Sr. ASIC EngineerJob Title - Sr. ASIC Engineer

ComTec Information SystemsCompany Name - ComTec Information Systems

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Odenton, Maryland, USA

Contract

Work Shift: 1st Shift (9/80A) Looking for an ASIC engineer to validate the performance of a high speed ASIC at our Aviation Blvd facility in Baltimore, MD. The ASIC is tested using a Stratix 10 FPGA and requires that the qualified candidate have experience of writing Matlab code and VHDL to generate commands to control and capture results. Familiarity with operation of High Speed Interfaces like a SerDes is required. Responsibilities: Conduct testing of ASIC in the lab utilizing the FPGA which i

Senior ASIC Design EngineerJob Title - Senior ASIC Design Engineer

PeopleNTechCompany Name - PeopleNTech

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San Jose, California, USA

Contract, Third Party

Position: Senior ASIC Design Engineer Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. Colla

Sr. ASIC Design Verification Engineer, Kuiper Modem DV TeamJob Title - Sr. ASIC Design Verification Engineer, Kuiper Modem DV Team

Amazon Kuiper Manufacturing Enterprises LLCCompany Name - Amazon Kuiper Manufacturing Enterprises LLC

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Austin, Texas, USA

Full-time

Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.The Role:Be part of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a wireless solution with few legacy constraints. The team works with c

Senior ASIC Design EngineerJob Title - Senior ASIC Design Engineer

PeopleNTechCompany Name - PeopleNTech

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San Jose, California, USA

Contract, Third Party

What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.Option to engage in block-level RTL design or block or top-level IP integration.Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the S

ASIC & FPGA Design EngineeringJob Title - ASIC & FPGA Design Engineering

Judge Group, Inc.Company Name - Judge Group, Inc.

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Orlando, Florida, USA

Full-time

Location: Orlando, FL Description: Role - Asic & Fpga Design Engineering Type: Contract Location - ( Onsite) Job Description: Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses spe

ASIC/FPGA Research Engineer - Digital DesignJob Title - ASIC/FPGA Research Engineer - Digital Design

University of Southern CaliforniaCompany Name - University of Southern California

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Arlington, Virginia, USA

Full-time

USC's Information Sciences Institute (ISI), a unit of the university's Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications and artificial intelligence technologies. ISI's 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Arlington, VA; Marina Del Rey, CA; and Waltham, MA. Perform digital hardware design in a fast-movin

Senior ASIC Engineer, Static Timing AnalysisJob Title - Senior ASIC Engineer, Static Timing Analysis

Infobahn Softworld Inc.Company Name - Infobahn Softworld Inc.

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Santa Clara, California, USA

Contract, Third Party

Role Title: Senior ASIC Engineer, Static Timing Analysis Location: San Jose, CA Onsite Alternate location: Colorado office - Longmont Duration: 12+ months contract Description: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA tool competence and Tcl based scrip

FPGA/ASIC Design SpecialistJob Title - FPGA/ASIC Design Specialist

Rolls RoyceCompany Name - Rolls Royce

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Indianapolis, Indiana, USA

Full-time

Job Description Job Title: FPGA/ASIC Design Specialist Working Pattern: Full-time Working location: Indianapolis, IN or West Lafayette, IN (Hybrid Work Schedule) Rolls-Royce is looking for a FPGA/ASIC (Field Programmable Gate Arrays / Application Specific Integrated Circuit) Design Specialist to join our growing team. This is an exciting opportunity to work on flagship Rolls-Royce programs and play a vital role in solving some of the most complex and interesting technological challenges in

Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASICJob Title - Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASIC

Motion Recruitment Partners, LLCCompany Name - Motion Recruitment Partners, LLC

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Irvine, California, USA

Full-time

Our client is a glbal infrastructure technology leader built on more than 60 years of innovation within the semiconndutor and Manufacturing space for communications. They are urgently seeking a Sr. level Digital Signal Processing (DSP) R&D Engineer to join their growing team. Responsibilities include: Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation Develop and

Senior ASIC Hardware EngineerJob Title - Senior ASIC Hardware Engineer

BlackFern RecruitmentCompany Name - BlackFern Recruitment

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Cambridge, Massachusetts, USA

Full-time

Security clearance: Applicants selected for this position will be required to obtain and maintain a government security clearance. Role: A Senior ASIC Hardware Engineer specifies, designs, verifies, tests, and documents Application-Specific Integrated Circuits. The engineer develops the architecture, designs circuits and/or HDL, performs simulations, performs physical layout, verifies and tests designs. Job Description: Duties/Responsibilities Design and simulate circuits at transistor-level to

ASIC Microarchitect EngineerJob Title - ASIC Microarchitect Engineer

APN Software Services, IncCompany Name - APN Software Services, Inc

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Irvine, California, USA

Full-time

Please contact Abdul on "" OR email me at "" Job Summary: As an ASIC Microarchitect, you will play a key role in designing and implementing state-of-the-art digital systems, SoCs, and high-performance RISC-V cores. You will collaborate closely with systems, software, and hardware design teams, as well as the physical implementation team, to architect microarchitectures that optimize power, performance, and area (PPA). We are looking for an innovative thinker who balances pragmatic engineering so

ASIC EngineerJob Title - ASIC Engineer

AdientOne LLCCompany Name - AdientOne LLC

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California, USA

Contract

Role: ASIC Engineer Location: Clara CA 95054 OR Longmont CO 80503 Duration: 12+months Job Description: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scrip

Senior ASIC Design Engineer- Emulation (HAPS Engineer)Job Title - Senior ASIC Design Engineer- Emulation (HAPS Engineer)

CloudiousCompany Name - Cloudious

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San Jose, California, USA

Contract

Position: Senior ASIC Design Engineer- Emulation (HAPS Engineer) Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top

ASIC Engineer, Formal VerificationJob Title - ASIC Engineer, Formal Verification

VeearCompany Name - Veear

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Sunnyvale, California, USA

Contract

Requirements: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.5+ years of experience in Formal VerificationExperience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etcProven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniquesProven analytical skills to craft Client solutions to tackle industry-le

ASIC/RTL Design Engineer - Senior at San Jose, CAJob Title - ASIC/RTL Design Engineer - Senior at San Jose, CA

Infobahn Softworld Inc.Company Name - Infobahn Softworld Inc.

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Santa Clara, California, USA

Contract, Third Party

TOP 3 SKILLS: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have KEY RESPONSIBILITIES: Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements. Collaborate with architecture and hardware teams to understand the requirements. Work with verification and p

FPGA/ASIC Verification EngineerJob Title - FPGA/ASIC Verification Engineer

Russell, Tobin & AssociatesCompany Name - Russell, Tobin & Associates

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No location provided

Contract

Job Title: FPGA/ASIC Verification Engineer Duration : 6 months with possible extension Pay range : $85-100/hr. on W2 (DOE) Location - Hybrid, Goleta, CA Client - Fortune 25 company. Work Schedule: Normal PST business hours, Monday - FridayProject Overview: The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to driven the internal components and send data. Overall Responsibilities: As a FPG

STA engineerJob Title - STA engineer

Sriven Systems Inc.Company Name - Sriven Systems Inc.

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Longmont, Colorado, USA

Contract

PREFERRED EXPERIENCE: 10+ years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high performance designs.Demonstrated ability in areas of ASIC STA constraints generation, timing analysis, timing convergence, and ECOs, at both block and full chip level, is a mustImplementation experience and knowledge handling multi-voltage design is expected. STA closure of low power and multi-power mode designs is an added advantage.Expertise in ind