ASIC Verification Engineer

We are seeking a Senior / Principal ASIC Designer to lead micro-architecture and RTL implementation for a high-performance scale-up switch ASIC. This role focuses on translating architecture into high-quality RTL optimized for advanced nodes. Key Responsibilities - Define micro-architecture for key blocks - Develop RTL using SystemVerilog and Verilog - Optimize for power, performance, and area - Implement high-speed datapaths and pipelines - Work with physical design for timing closure - Supp

Location:REMOTEDuration: ~12 months (Immediate start through Q1 next year)Team Size: ~10 Engineers (Mix ofDesign & DV )Question from hiring manager on prior submital: Can you also check with the candidates on their recent hands-on experience with RTL design using SystemVerilog, & working on IPs with multiple clock domains?1. RTLDesignEngineerKey ResponsibilitiesOwn micro-architecture definition from high-level functional specificationsDevelop and implement RTL for complex digital blocksDrive dig

Location: Longmont, CO LOA: Up to 1 year on the contract The 93k environments are SmarTest 8&7. Key Responsibilities Develop, debug, and optimize test programs on Advantest V93000 SoC test systems (SmarTest 8 & 7) Perform silicon characterization, production test bring-up, and yield analysis. Work on digital and mixed-signal SoC testing in ATE environments. Analyze test failures and perform root-cause debugging. Collaborate with design, DFT, validation, and product engineering teams to improve

Quick feedback One to two interview process Microsoft Teams MUSTbe able to work onsite inSanta Clara no exceptions Key points: UVM Systemverilog 10+ years of exp Onsite in Santa Clara 1 year We are looking forstrong SoC DVcandidates to work onsite in San Jose. System-level experience is highly preferred. Familiarity withAXI4 is preferred Strong SystemVerilog and UVM skillsScripting experience (Python/Perl/Shell) is a plusC-based programming experience is a strongplusExperience with infrastru