Ottawa, Ontario
•
Today
We are seeking a Senior / Principal Verification Engineer to lead verification architecture and execution for a next-generation scale-up switch ASIC (~500mm , TSMC 3nm/2nm). This role is critical to ensuring first-pass silicon success for a high-bandwidth, low-latency interconnect targeting AI and HPC systems. Key Responsibilities - Define full-chip and subsystem verification strategy - Architect scalable UVM environments - Develop SystemVerilog/UVM testbenches - Define and drive coverage closu
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Contract
Depends on Experience


