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Role Senior Design Verification Engineer / PCIe (either IP or SoC level experience) Location- Remote, US Job Type Full-Time Required Skills: experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UV
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Full-time
$180,000 - $200,000