tcl Jobs

161 - 177 of 177 Jobs

Low Power Principal Engineer/ASIC EngineerJob Title - Low Power Principal Engineer/ASIC Engineer

SivaltechCompany Name - Sivaltech

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San Diego, California, USA

Full-time, Third Party

"Exciting Opportunity! We're seeking a Low Power Principal Engineer/ASIC Engineer to join our team in San Diego, CA! Key Responsibilities: - Low power design and verification (UPF, VCLP) - Power analysis and optimization (PTPX) - STA and timing analysis - Synthesis and physical design (DC synthesis) Requirements: - 5+ years of experience in ASIC design, low power design, and verification - Proficiency in scripting languages (Shell, TCL, Perl, Python) - Experience with VCLP, PTPX, Formality,

ASIC Design EngineerJob Title - ASIC Design Engineer

Yochana IT SolutionsCompany Name - Yochana IT Solutions

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Santa Clara, California, USA

Contract, Third Party

ASIC Design Engineer Location: Santa Clara, CA Onsite Contract Overview of the Role As an ASIC Design Engineer , you will play a crucial role in the development and optimization of our cutting-edge ASIC solutions. Your work will directly impact the efficiency, performance, and scalability of our products, driving forward the company's objectives and contributing to technological innovations that shape the industry. Detailed Responsibilities Run and manage Fusion Compiler, ICC II, and Innovus

ASIC STA & CAD EngineeringJob Title - ASIC STA & CAD Engineering

Coretek LabsCompany Name - Coretek Labs

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Longmont, Colorado, USA

Full-time, Third Party, Contract

Job Title: ASIC STA & CAD Engineering Location: Longmont, Colorado (Hybrid) Duration: Long Term Contract Domain: Engineering Key Responsibilities: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Engaging closely with block and SoC design teams to understand the design

STA EngineerJob Title - STA Engineer

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery. Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates Synthesis Tools: Synopsys DC/DCG/FC. Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cade

DFT/DFX EngineerJob Title - DFT/DFX Engineer

Mirafra IncCompany Name - Mirafra Inc

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Austin, Texas, USA

Full-time

Experience with Scan Shift Network is required. Experience with Tessent is highly desired. Good exposure to scripting with Tcl/Perl Responsibilities: Steer the Automation for SSN enablement Understand SOC requirements and project milestones to help define a DFT architecture which optimally balances between coverage, test-time, and execution. Create a detailed implementation spec which documents details of the architecture including SOC-level interface, clock design, and support of various test/d

RTL Engineer: Integrate RISC-V Core to SoCJob Title - RTL Engineer: Integrate RISC-V Core to SoC

Intelliswift Software IncCompany Name - Intelliswift Software Inc

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Santa Clara, California, USA

Contract

Job Title: RTL Engineer: Integrate RISC-V Core to SoC Location(s): Santa Clara, CA - Onsite Must Have skills: 5+ years of experience in RTL design, SoC integration, or related areas.Strong hands-on experience with hardware description languages (Verilog, SystemVerilog, VHDL), EDA tools, and simulators (VCS, NC, Verilator).Deep understanding of SoC design, integration, and high-performance interfaces (e.g., AXI, TileLink, PCIe, Ethernet).Proven ability to debug and optimize designs for functiona

F5 Load Balancing EngineerJob Title - F5 Load Balancing Engineer

Euclid InnovationsCompany Name - Euclid Innovations

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Fort Mill, South Carolina, USA

Third Party, Contract

Job Title: F5 Load Balancing Engineer Location: Fort Mill, SC (Hybrid) Duration: Long-term Job Description: We are seeking a highly skilled F5 Load Balancer Engineer with expertise in F5 iRules, Load Balancing, and Application Traffic Management. The ideal candidate will be responsible for designing, implementing, and maintaining load balancing solutions to ensure high availability, performance, and security for enterprise applications. Required Skills & Qualifications: 10+ years of hands-on ex

F5 Load Balancer EngineerJob Title - F5 Load Balancer Engineer

Euclid InnovationsCompany Name - Euclid Innovations

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Charlotte, North Carolina, USA

Contract, Third Party

Job Title: F5 Load Balancer Engineer Location: Charlotte, NC Duration: Long-term Job Description: We are seeking a highly skilled F5 Load Balancer Engineer with expertise in F5 iRules, Load Balancing, and Application Traffic Management. The ideal candidate will be responsible for designing, implementing, and maintaining load balancing solutions to ensure high availability, performance, and security for enterprise applications. F5 Req: Expertise in F5 Device VIP/Pool Add Modify Solid knowledge

Infra Silicon Physical Design EngineerJob Title - Infra Silicon Physical Design Engineer

CloudiousCompany Name - Cloudious

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Sunnyvale, California, USA

Contract, Third Party

Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin, TX Duration: 12 Months Qualification/Experience/Skills Required: - Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes - Hands-on experience with block level physical design (Floor planning to GDSII) - Experience with SoC level integration (multiple blocks, SoC floorplan, clocking, and timing analysis) preferred - Expertise in

Static Timing Analysis EngineerJob Title - Static Timing Analysis Engineer

CloudBlue TechnologiesCompany Name - CloudBlue Technologies

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San Jose, California, USA

Full-time

Title: Static Timing Analysis Engineer Location: San Jose, CA Duration: One Year Plus - Onsite PR Range: $65 - $70 /hr on W2 or $72 - $75 on C2C. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location). Job Description: We are looking for a Static Timing Analysis Engineer with atleast 8 years of experience in Functional and test timing constraints, Static Timing Analysis, Primetime , RTL Codin

Power Engineer-PTPXJob Title - Power Engineer-PTPX

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Work closely with the Design, DV, Implementation team to define low power vectors, generate early and signoff power data using PTPX or any other low power tool.Analyze power data, and work closely with PD and design team to optimize for low power and improve overall PPA.Support in enhancing low power flows, work with tool vendors to address any power-related tool or flow issues.Hands-on skills in one of the scripting languages, Shell/TCL/Perl/PythonExperience with correlating pre-silicon power e

Senior Manager / ASIC STA & CAD EngineeringJob Title - Senior Manager / ASIC STA & CAD Engineering

Coretek LabsCompany Name - Coretek Labs

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Longmont, Colorado, USA

Contract, Third Party

ASIC Engineer (Design Verification)Job Title - ASIC Engineer (Design Verification)

CloudiousCompany Name - Cloudious

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Sunnyvale, California, USA

Contract, Third Party

ASIC Engineer (Design Verification) Bay Area, CA or Austin, TX 12 Months Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collab

SYSTEMS ENGINEER - TEST - AMMOLITE PROGRAM - LINTHICUM MD - 13885Job Title - SYSTEMS ENGINEER - TEST - AMMOLITE PROGRAM - LINTHICUM MD - 13885

ASD, Inc.Company Name - ASD, Inc.

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Linthicum Heights, Maryland, USA

Contract

SYSTEMS ENGINEER - TEST - AMMOLITE PROGRAM - LINTHICUM MD Space Systems in Linthicum, MD is seeking a Test Engineer to support on-site, 1st, 2nd, and 3rd shift test bench operations for the Assembly, Integration and Test (AI&T) of a production Space Payload program. Responsibilities include executing test scripts for the verification of Software, Hardware, and System requirements for applications in Space. Understanding of RF (Radio Frequency) systems, especially RADAR, SIGINT, or COMMS; program

Senior FPGA Design Verification Engineer - Secret ClearanceJob Title - Senior FPGA Design Verification Engineer - Secret Clearance

Amarx Search, Inc.Company Name - Amarx Search, Inc.

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Dedham, Massachusetts, USA

Full-time

Amarx Search, Inc. - amarx.com Direct Hire - Full Time position in Dedham, MA Position ID: 2632 An excellent position with a major global technology solutions company * Senior FPGA Design Verification Engineer - Secret Clearance * Please apply ONLY if you have an active DOD Secret clearance and VHDL (or similar) United States Citizenship is required due to government contract requirement; we are unable to sponsor at this time. We can ONLY consider your application if you have: 1: Active DOD Sec

Teamcenter Systems Engineering ManagerJob Title - Teamcenter Systems Engineering Manager

Capgemini Government SolutionsCompany Name - Capgemini Government Solutions

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McLean, Virginia, USA

Full-time

Capgemini Government Solutions (CGS) LLC is seeking highly motivated and experienced Teamcenter Systems Engineering Manager to join our team to support our government clients. The successful applicant will play a crucial role in implementing and maintaining our Teamcenter Systems Engineering solutions, ensuring flawless integration and performance. Opportunity to enhance abilities, collaborate with a driven team, interact with various collaborators, and strengthen CGS? capacity to support client

ASIC Verification EngineerJob Title - ASIC Verification Engineer

Yoh - A Day & Zimmerman CompanyCompany Name - Yoh - A Day & Zimmerman Company

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Remote or Monte Sereno, California, USA

Full-time

ASIC Verification Engineer Reviewing the product designs and noting likely points of failure. Designing verification methodology based on product designs and failure points. Determining testing environments and verification tools. Planning the method of sequence for testing operations. Instituting and tweaking testing mechanisms and protocols. Writing up final test procedures and training QC staff. Qualificatios Bachelor s or Master s in Electrical or Computer Science 4 years of Design Verificat