Overview
On Site
$160,000 - $180,000
Full Time
Accepts corp to corp applications
No Travel Required
Able to Provide Sponsorship
Skills
ASIC
Static Timing Analysis
Physical Data Model
Scripting
Python
UPF
VCLP
PTPX
Job Details
"Exciting Opportunity!
We're seeking a Low Power Principal Engineer/ASIC Engineer to join our team in San Diego, CA!
Key Responsibilities:
- Low power design and verification (UPF, VCLP)
- Power analysis and optimization (PTPX)
- STA and timing analysis
- Synthesis and physical design (DC synthesis)
Requirements:
- 5+ years of experience in ASIC design, low power design, and verification
- Proficiency in scripting languages (Shell, TCL, Perl, Python)
- Experience with VCLP, PTPX, Formality, LEC, and DC synthesis
What We Offer:
- Competitive salary and benefits package
- Opportunities for professional growth and development
- Collaborative and dynamic work environment
If you're passionate about low power design and ASIC engineering, let's connect! "
We're seeking a Low Power Principal Engineer/ASIC Engineer to join our team in San Diego, CA!
Key Responsibilities:
- Low power design and verification (UPF, VCLP)
- Power analysis and optimization (PTPX)
- STA and timing analysis
- Synthesis and physical design (DC synthesis)
Requirements:
- 5+ years of experience in ASIC design, low power design, and verification
- Proficiency in scripting languages (Shell, TCL, Perl, Python)
- Experience with VCLP, PTPX, Formality, LEC, and DC synthesis
What We Offer:
- Competitive salary and benefits package
- Opportunities for professional growth and development
- Collaborative and dynamic work environment
If you're passionate about low power design and ASIC engineering, let's connect! "
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