verilog Jobs - Page 19

Design Verification EngineerJob Title - Design Verification Engineer

JConnect IncCompany Name - JConnect Inc

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San Jose, California, USA

Full-time

Role: Design Verification Engineers (SoC-5, PCIe-5)Location: Bay AreaSalary: 160-240k (DOE) Free health insurancePTOs: 10 Business days (Including sick leaves) Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium) Job Description: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from speci

Design Verification EngineerJob Title - Design Verification Engineer

Xoriant CorporationCompany Name - Xoriant Corporation

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Austin, Texas, USA

Contract

Job Title: Design Verification Engineer #368877 Duration: 12+ months (Possible Extension-Long Term Project) Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite) Description As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updatesDebug functional errors in RTL model using simulation and debug tools.Maintain efficient and clean re