Verilog jobs | Dice.com

Sunset Valley, Texas

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Yesterday

Job Description:Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)Strong proficiency in System Verilog Assertions (SVA) and formal property specificationExperience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysisFamiliarity with scripting languages (TCL, Python, Perl) for flow automationExtensive experience in design verification with a strong focus on formal verificationExpertise in Syst

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Third Party, Contract

Depends on Experience

Verification Engineer in CA and TX

San Francisco, California

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11d ago

Hi, I hope all is well. I am doing a search for a client who has an urgent requirement for a network administrator contract opportunity. The job description is listed below. If this is something you are interested in, please call me ASAP at . please mail me your updated resume in Word format, availability, contact details, and hourly rate as per the hiring policy of our client. ASIC Verification Engineer About the role: PCIe Protocol IP Verification Expert: Consulting & Turnkey projec

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Contract, Third Party

Depends on Experience

Verification Engineer

Hybrid in Santa Clara, California

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10d ago

Role: Verification Engineer Location: Santa Clara, CA & Contract Job Description: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test p

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Contract

Depends on Experience

Hardware Design Engineer

Hillsboro, Oregon

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional HW Design Engineer to join our MCG team in Hillsboro. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per w

Full-time

USD 106,900.00 - 198,500.00 per year

SoC Design Verification Engineer

San Jose, California

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15d ago

Position Title: SoC Design Verification Engineer Location: San Jose, CA Remote/Onsite: Onsite Types of Hire: Fulltime Job Description: - We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets. Key Responsibilities: Develop and execute S

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Full-time, Third Party

Depends on Experience

Senior ASIC RTL DESIGN Engineer

Remote or Hybrid in Boston, Massachusetts

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22d ago

12 Months + CONTRACT Starting in September SKILLS: SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Prefer experience with some of: LPDDR5 UFS/FlashPCIe Gen4/5

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Contract

90 - 130

Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)

San Jose, California

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9d ago

Role: Principal/Lead Design Engineer Memory Controller- (CHI-G / DFI) Location:San Jose, CA Lets create our future together at The AES Group! About The AES Group The AES Group is a premier technology and engineering consulting company that has been bringing businesses and talent together for over 20 years to deliver innovative solutions that have the greatest positive impact on society. AES has helped over 40 business enterprises, including Fortune 500 companies, engage their customers,

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Contract, Third Party

Depends on Experience

DFT Engineer

Santa Clara, California

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9d ago

Job Title: DFT Engineer Location: Santa Clara, CA Work Arrangement: Onsite Experience: 5+ Years JOB DESCRIPTION We are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer to contribute to complex ASIC/SoC designs and next-

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Third Party, Contract

80 - 100

RTL Engineer, Networking ASIC

Saratoga, California

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9d ago

Qualifications ME/BE with a minimum of 8-15 years of experience.Hands-on knowledge of SystemVerilog and Verilog is mandatory.Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.Proven expertise in designing and optimizing scheduling and QoS mechanisms.Experience with Ethernet and IP protocols.Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking i

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Full-time

200000 - 220000

Sr. Asic Design Verification Engineer

Hybrid in Austin, Texas

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18d ago

Job Title: Senior ASICDesignVerificationEngineerLocation:Austin, TX (Onsite/Hybrid) Experience:15+ YearsJob SummaryWe are seeking an experiencedSenior ASICDesignVerificationEngineerto verify next-generation CPU, AI/ML,andSoCdesigns. The ideal candidate will have strong expertise in developingUVM-basedverificationenvironments, functional coverage, RTL debug,andconstrained-randomverificationwhile working closely withdesignandarchitecture teams from specification through tape-out.Primary Skills (Mu

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Contract, Third Party

Depends on Experience

DFT MBIST Staff Engineer

Remote

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Yesterday

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SM

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Contract, Third Party

85 - 90

Mixed Signal Verification Engineer

San Jose, California

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Yesterday

Job Responsibilities: Creating AMS/DMS testbench for wireless RF and High Speed PHY.Working with RF/Analog design engineers for analog circuit modelsSupport silicon bring-up and commercialization. Required Skills: BS or BE minimum, 3+ year experiences Deep understanding of digital VLSI simulation flow Deep understanding of mixed-mode and analog simulation flow Experience with Verilog/SystemVerilog and RNM modeling Experience with digital verification, UVM, and waveform debug Teamwork, dedication

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Contract

94 - 155

Senior FPGA Engineer

Chandler, Arizona

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3d ago

Senior FPGA Engineer Location: Chandler, AZ (Onsite 5 days/week) Position SummaryWe are seeking a Senior FPGA Engineer with experience across the entire design flow for complex FPGAs to lead the design, development, and debugging of FPGA SoC systems supporting advanced satellite communications technologies. This role focuses on advanced IP integration, high-performance RTL development, and userspace driver/firmware development. ResponsibilitiesDesign, develop, document, debug, and test FPGA SoC

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Full-time

$120000 - $150000

Senior Electrical Engineer - Analog, Power, FPGA

Odenton, Maryland

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4d ago

Amarx Search, Inc. - amarx.com Direct Hire - Full Time position in Millersville, MD Pay: Level 4 position: $106,500 to $197,500 based on relevant experience Level 5 position: $127,500 to $236,500 based on relevant experience Position ID: 2736 An excellent position with a large defense technology company delivering innovative mission solutions * Senior Electrical Engineer * Please apply ONLY if you have advanced skills in analog, power, and FPGA design United States Citizenship is required due t

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Full-time

$106,500 - $236,500

DFT Engineer Intern

No location provided

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Today

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description Position Responsibilities: Logic Design to support DFT featuresAutomate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoCVerification of DFT Logic and analysis of fault coverageTiming analysis for DFT Modes Minimum Requirements: MSEE in Electrical / Computer EngineeringKnowledge of DFT fundamentalsKnowledge of

Full-time

FPGA Engineer

Melbourne, Florida

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Today

Required Skills: Expert-level verification engineer with strong SystemVerilog and/ or UVM experience orFPGA verification in lab testing and/or Hardware FPGA design verification testingExperience with design on Xilinx products would be a strong plusexpected to communicate effectively with emerging engineers at the India GETC-I site and provide both technical and process (DO-254) guidance to the verification team. Core Responsibilities RTL Design & Simulation: Develop code and testbenches using VH

Full-time

Senior FPGA Design Engineer

Tempe, Arizona

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Today

RESPONSIBILITIES: Kforce's client, an innovative technology company based in Tempe, AZ, is seeking a Senior FPGA Design Engineer to join a highly technical engineering team. This role offers the opportunity to design and implement advanced FPGA-based digital systems and contribute to complex, multidisciplinary engineering projects. Responsibilities include the design and implementation of FPGA-based digital systems and architecture and developing high-speed signal-processing algorithms and crypt

Full-time

$165,000 - $185,000 annually

RTL Engineer

Washington

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Today

As a RTL Engineer, a typical day might include the following: Invents, analyzes and designs complex analog and digital circuits to meet specifications. Lead hardware design reviews to demonstrate product and circuit robustness.Leads in the development of hardware and system level specifications of moderate complexity.Writes and reviews test plans, executes or supervises testing, evaluates and reviews test results for use in peer reviews and for project notebooks.Prepares and maintains accurate p

Full-time

USD 136,080.00 - 201,050.00 per year

Verification Engineer

Saratoga, California

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9d ago

Qualifications ME/BE in Electrical Engineering, Computer Engineering, or related field.Experience:A MINIMUM of8-15 years in ASIC verification in the area of data center networking.Verification Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM/VMM/UVM) with a strong understanding of ASIC Design and Verification flow. Experience with functional coverage, gate/timing/power simulations, constrained random verification and test-plan documentat

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Full-time

150000 - 200,000

Hardware Engineer (FPGA/ASIC)

New York, New York

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Today

About the Position Our goal is to give you a real sense of what it's like to work at Jane Street full time while also providing a truly unparalleled educational experience. As an intern, you are paired with full-time employees who act as mentors, collaborating with you on real-world projects we actually need done. In this internship, you'll learn how we use tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our hardware engineering work, and w

Full-time