Verilog jobs | Dice.com

Ben Lomond, California

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26d ago

JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run du

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Third Party, Contract

Depends on Experience

DFT Engineer

California

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Today

Job Title: DFT Engineer Location: Saratoga, CA (Onsite) Duration: Contract & Full-Time Job Description: Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG). Proficiency in Synthesis design constraints. ( Ie SDC) Prior experience with Serializers/Deserilizers. Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis, Define and implement OCC. Exposure to

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Full-time

Hardware Design Engineer

Hillsboro, Oregon

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional HW Design Engineer to join our MCG team in Hillsboro. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per w

Full-time

USD 106,900.00 - 198,500.00 per year

ASIC Engineering Technical Leader

San Jose, California

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Today

Role: ASIC Engineering Technical Leader Location: San Jose, CA (Onsite) Start Date: Immediate Type: Contract (C2C/W2) Interview: Phone/Video We are seeking an ASIC Engineering Technical Leader with strong expertise in DesignforTest (DFT) for nextgen optical communication ASICs. Responsibilities include DFT architecture implementation, scan insertion, ATPG pattern generation, silicon debug, integration/verification of DFT fabrics, gatelevel simulations, and automation using Python/Tcl/C++.

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Full-time, Part-time, Contract, Third Party

Field Programmable Gate Array

Ben Lomond, California

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19d ago

Job Description: This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The PersonStrong analyt

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Third Party, Contract

Depends on Experience

Design Engineer II # 26-23167

Remote

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20d ago

Duration: 8 Months Contract Summary: Overview Contract digital design engineer to integrate the lowspeed peripheral subsystem I3C, I2C, SPI/QSPI/OSPI, UART controllers including the IO cells, pad ring connectivity and IO multiplexing that these peripherals depend on. Duties Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top Own IOlevel integration: pad/IO cell selection and configuration, IO mux design and programmability, pullup/pulldown, drive

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Contract

$70 - $150

Design Engineer II # 26-23166

Remote

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20d ago

Duration: 8 Months Contract Summary: A contract digital design engineer to own integration of the camera ingest path MIPI C/DPHY and CSI2 receivers into the image signal processing (ISP) pipeline including development of the glue logic required to bridge CSI2 and ISP interfaces. Duties:Integrate MIPI CPHY/DPHY, CSI2 controller and ISP IPs at subsystem and chip levelDesign and code the glue logic between CSI2 output and ISP input: stream/virtualchannel handling, datatype unpacking, line/frame

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Contract

$70 - $150

DFT Engineer Intern

No location provided

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Today

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description Position Responsibilities: Logic Design to support DFT featuresAutomate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoCVerification of DFT Logic and analysis of fault coverageTiming analysis for DFT Modes Minimum Requirements: MSEE in Electrical / Computer EngineeringKnowledge of DFT fundamentalsKnowledge of

Full-time

ASIC Design Engineer

Mountain View, California

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2d ago

Hi , This role is a Full Time / Permanent . Title: Senior ASIC / SoC Network-on-Chip Design Engineer or Senior ASIC Design Engineer Location : Mountain View CA Qualifications 8+ years delivering ASIC/SoC IP designs. 6+ years of hands-on digital design, RTL, and microarchitecture experience. Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs. Experience with NoC/interconnect and high-throughput/low-latency designs. Experience with SoC

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Full-time

Depends on Experience

FPGA Intern Engineer

Manassas, Virginia

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Today

Basic Qualifications Candidates should demonstrate a thorough understanding of engineering technology. Engineering Interns must be enrolled in an accredited degree program in Computer Engineering, Systems Engineering, Software Engineering, Electrical Engineering, Mechanical Engineering or other related scientific or technical discipline with a preference for a standing of a sophomore or higher. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibil

Full-time

USD 24.70 - 30.45 per hour

Mixed Signal Engineer Intern

No location provided

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Today

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description Job description: As a member of the Mixed Signal team, the candidate will work with senior circuit designers in the design, validation and characterization of mixed signal and analog IP blocks for SOC. The IPs include PLL, DLL, SERDES, high speed IO and data converters, etc. for sub-14nm technologies. The candidate will have exposure to

Full-time

FPGA Engineer

Melbourne, Florida

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Today

Required Skills: Expert-level verification engineer with strong SystemVerilog and/ or UVM experience orFPGA verification in lab testing and/or Hardware FPGA design verification testingExperience with design on Xilinx products would be a strong plusexpected to communicate effectively with emerging engineers at the India GETC-I site and provide both technical and process (DO-254) guidance to the verification team. Core Responsibilities RTL Design & Simulation: Develop code and testbenches using VH

Full-time

ASIC/SoC Verification Architect – Short Supplier

St. Louis, Missouri

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6d ago

Key Requirements: 10+ years of experience in ASIC/SoC verification and verification architecture. Strong hands-on SystemVerilog, UVM, Verilog, and constrained-random verification. Experience developing verification strategies, test plans, testbenches, coverage models, and verification environments. Strong knowledge of SoC architecture, RTL, CPU/processor, interconnects, memory, and IP verification. Experience with UVM/SystemVerilog assertions, functional/code coverage, simulation, and debugging.

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Contract

Up to 160

Electronic Design Engineer

Fort Worth, Texas

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Today

Job Summary: - Assist with the development, design, testing and certification documentation for new or modified printed circuit board modules for aircraft - Apply electrical engineering theory and the operation of electronic test equipment to test and troubleshoot avionics / electrical modules or systems - Model and simulate electronic circuits using SPICE software - Design printed circuit board layouts using Altium design software - Modify and maintain programmable logic designs in FPGAs an

Full-time

Lead Functional Product Engineer, Power Analysis

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments. Key Responsibilities Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages Reproduce, debug, and resolve customer-reported issues in power an

Full-time

USD 114,800.00 - 213,200.00 per year

CPU Physical Design Engineer, San Diego

San Diego, California

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what\'s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engine

Full-time

Compensation information provided in the description

Verification Engineer Intern

No location provided

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Today

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description Ambarella has some exciting internship opportunities for self-motivated and creative students near completion of their master's degree. We are looking for talented engineers who possess a strong interest in VLSI design, programming and computer architecture. Ambarella designs complex SoCs which include custom DSP and computer vision bloc

Full-time

Graphics (GPU) Performance Analysis Engineer

Austin, Texas

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Yesterday

Do you love creating elegant solutions to highly complex challenges? In our Silicon Technologies group, we help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will en

Full-time

Silicon Prototyping Engineer

Cupertino, California

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Yesterday

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practice

Full-time

Validation CAD Engineer

Austin, Texas

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Yesterday

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the tech

Full-time