We do have a DFT -Technical Lead role in Dallas, TX(Onsite). Please find the Job Description below and kindly respond back with your updated resume. Job Title: DFT -Technical Lead Job Location: Dallas, TX(Onsite) Duration: 12+ Months Job Description: Understanding the DFT architecture and specification, work from insertion, verification, pattern generation, working with PE till production needs to be done. Skills Required: DFT strong backgroundScan insertion (Block and top)MBIST insertion (Bloc
Role/ Responsibilities: Understanding the DFT architecture and specification, work from insertion, verification, pattern generation, working with PE till production needs to be done. Along with he/she needs to lead the 2 engineers needs . Skills Required: DFT strong background Scan insertion (Block and top) MBIST insertion (Block and top) OCC insertion and EDT insertion iJTAG implementation etc
Description: Responsible for doing all aspects of SOC Physical Design implementation. For this position, the candidate will be representing Synopsys under our Design Services organization working on physical design implementation for SOC programs our customers have contracted to Synopsys. Some programs can be working with Synopsys team members and others can be customer augmentation with well-defined responsibilities. The ideal candidates should be highly proficient in using all the Synopsys EDA
Senior RTL Designer Engineer. Full-time opportunity inCampbell, CA(100% remote considered). Responsibilities Develop and execute: micro-architecture specification, RTL in Verilog/System Verilog, performance, speed, power goals, and verificationBringing up the chip in lab and developing bring-up scriptsParticipate in chip architecture definition, review, verification, and testingRequirements BS/MS in Electrical Engineering or Computer Engineering with 5+ years of relevant experience from design
