Search Jobs | Dice.com

12 results (0 new)

Group by company

Asic Chip Lead-Full Time- Onsite

Technical Link

Brooklyn Park, Minnesota • 4d ago

Easy Apply

Full-time

145,000 - 205,000

ASIC Chip Lead / Design Engineer

Technical Link

Brooklyn Park, Minnesota • 5d ago

Easy Apply

Full-time

145,000 - 205,000

Lead Engineer - Network Operating System, Software Developer

Target Corporation

Brooklyn Park, Minnesota • Today

Full-time

USD 132,000.00 - 238,000.00 per year

Senior ASIC RTL DESIGN Engineer

Carlton National Resources, INC

Remote or Hybrid in Boston, Massachusetts • 18d ago

Easy Apply

Contract

90 - 130

Lead ASIC DFT Engineer

SAPSOL Technologies Inc.

Remote • Today

Full-time

Lead AI Engineer with Machine Learning

EPAM Systems

Remote • Today

Full-time

Senior ASIC Emulation Engineer

K2 Space

Remote • Today

Full-time

USD 170,000.00 - 250,000.00 per year

Senior Principal ASIC FPGA Engineer

General Dynamics

Remote or Boise, Idaho • Today

Full-time

USD 191,146.00 - 212,053.00 per year

Senior FPGA Prototyping Engineer

K2 Space

Remote • Today

Full-time

USD 120,000.00 - 225,000.00 per year

Lead RTL/FPGA Design Engineer

Aalyria

Remote • Today

Full-time

USD 170,000.00 - 195,000.00 per year

Senior Java Full Stack Technical Lead Remote - Full-Time

Collaborate Solutions, Inc.

Remote • 14d ago

Easy Apply

Full-time

$50 - $60

Lead Engineer - Full Stack (Remote)

Progressive Leasing

Remote or Utah • Today

Full-time

Technical Link

Job Details

Skills

ASIC Design
SoC Design
SystemVerilog
ARM
ASIC
RTL
Synopsys design compiler
Verilog
System On A Chip
Place And Route
Mixed-signal Integrated Circuit
Digital Circuit Design
Digital Design
Electrical Engineering

Summary

Asic Chip Lead-Full Time- Onsite Brooklyn Park, MN

As an ASIC Chip Lead and Design Engineer, you will play a pivotal role in the development of custom-designed Application-Specific Integrated Circuits (ASICs). Your expertise will span the entire chip design lifecycle, from conceptualization to implementation. You’ll collaborate with cross-functional teams, ensuring successful chip development while adhering to performance, power, and area targets. The right candidate will be someone with high aptitude who is currently hands on designing complex digital blocks, with strong knowledge/experience across the complete ASIC/SOC design flow. An ideal candidate will additionally have experience with radiationhardened design, analog/mixed-signal design and EDA, and std-cell library development.

Additional duties include the evaluation of customer requirements and estimates of effort/expenses for potential new business, and participation in identifying problems with and improvements to, internal design methodologies.

Essential Duties and Qualifications:

Chip Architecture and Development:

Lead the architectural design of ASICs based on high-level requirements and block diagrams.
Collaborate with system architects to define chip functionality, interfaces, and performance targets.
Develop detailed specifications for the chip’s components.

RTL Design and Synthesis:

Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.
Optimize RTL code for area, power, and performance.
Implement and verify complex digital blocks.

Constraint Development:

Develop timing constraints for the entire chip.
Work closely with physical design teams to ensure successful place-and-route.  RISC Processor Conformance:
Constrain and verify RISC processors within the chip. o Optimize processor performance and power efficiency.

Physical Design Collaboration:

Collaborate with physical design teams on floorplanning, placement, and routing.
Address any design closure issues.

Verification Support:

Work with verification engineers to ensure functional correctness.
Assist in creating testbenches and verifying the chip’s functionality.

Modern revision-control tools and best-practices in a collaborative, multi-site design community.
Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g. sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting.
Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversion.

Qualifications:

Bachelors/master’s in electrical engineering/computer science or equivalent.
10+ years of direct industry experience with ASIC and/or SoC design.
Proficiency in Synopsys Design Compiler and other EDA tools.
Strong understanding of digital design principles.
Familiarity with RISC architectures (e.g., ARM, MIPS).
Excellent problem-solving skills and attention to detail.
A strong background in RTL based digital IC design using Verilog/SystemVerilog  Proven track record of first-pass successes.
A self-starter with the ability to assume leadership roles.
Ability to work well in a diverse team environment.
Willingness to Mentor less senior engineers.
Experience with industry standard development tools and methodologies.

Target annual salary:

The US base salary range for this full-time position is $145,000-$205,000.

Location:

Work on-site at the TSS office in Brooklyn Park, MN.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10308440
Position Id: 9068591
Posted 4 days ago

Company Info

About Technical Link

Technical-Link North America is dedicated to excellence in engineering staffing, connecting top talent with leading companies. Whether you're an employer seeking skilled engineers or an engineer looking for your next contract opportunity, we have the expertise and resources to meet your needs.

Go to company profile

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Contact the job poster

Lekenzey Siddell

Recruiter @ Technical Link

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

ASIC Chip Lead / Design Engineer

Brooklyn Park, Minnesota

•

5d ago

ASIC Chip Lead / Design EngineerJob DescriptionAs an ASIC Chip Lead and Design Engineer, you will play a pivotal role in the development of custom-designed Application-Specific Integrated Circuits (ASICs). Your expertise will span the entire chip design lifecycle, from conceptualization through implementation. You will collaborate with cross-functional teams to ensure successful chip development while meeting performance, power, and area targets. The ideal candidate is a highly capable, hands-on

Easy Apply

Full-time

145,000 - 205,000

PMIC Digital Design Engineer

Hybrid in Allen, Texas

•

4d ago

PMIC Digital Design Engineer Location: Allen, TX must be onsite at least 50% of the time Duration: 6-month contract Seeking an experienced Digital Design Engineer with a strong background in PMIC / Power Management IC design. Key Skills: PMIC / Power Management IC experienceVerilog RTLSystemVerilogDigital architecture / architecture definitionDigital controllers and sequencersClock management controllersDigital design verificationCandidates must be able to work onsite in Allen, TX at least 50%

Easy Apply

Contract

60 - 90

Technical Link

Job Details

Skills

ASIC Design
SoC Design
SystemVerilog
ARM
ASIC
RTL
Synopsys design compiler
Verilog
System On A Chip
Place And Route
Mixed-signal Integrated Circuit
Digital Circuit Design
Digital Design
Electrical Engineering

Summary

Asic Chip Lead-Full Time- Onsite Brooklyn Park, MN

Essential Duties and Qualifications:

Chip Architecture and Development:

Lead the architectural design of ASICs based on high-level requirements and block diagrams.
Collaborate with system architects to define chip functionality, interfaces, and performance targets.
Develop detailed specifications for the chip’s components.

RTL Design and Synthesis:

Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.
Optimize RTL code for area, power, and performance.
Implement and verify complex digital blocks.

Constraint Development:

Develop timing constraints for the entire chip.
Work closely with physical design teams to ensure successful place-and-route.  RISC Processor Conformance:
Constrain and verify RISC processors within the chip. o Optimize processor performance and power efficiency.

Physical Design Collaboration:

Collaborate with physical design teams on floorplanning, placement, and routing.
Address any design closure issues.

Verification Support:

Work with verification engineers to ensure functional correctness.
Assist in creating testbenches and verifying the chip’s functionality.

Modern revision-control tools and best-practices in a collaborative, multi-site design community.
Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g. sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting.
Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversion.

Qualifications:

Bachelors/master’s in electrical engineering/computer science or equivalent.
10+ years of direct industry experience with ASIC and/or SoC design.
Proficiency in Synopsys Design Compiler and other EDA tools.
Strong understanding of digital design principles.
Familiarity with RISC architectures (e.g., ARM, MIPS).
Excellent problem-solving skills and attention to detail.
A strong background in RTL based digital IC design using Verilog/SystemVerilog  Proven track record of first-pass successes.
A self-starter with the ability to assume leadership roles.
Ability to work well in a diverse team environment.
Willingness to Mentor less senior engineers.
Experience with industry standard development tools and methodologies.

Target annual salary:

The US base salary range for this full-time position is $145,000-$205,000.

Location:

Work on-site at the TSS office in Brooklyn Park, MN.

Dice Id: 10308440
Position Id: 9068591
Posted 4 days ago

Company Info

About Technical Link

Go to company profile

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Contact the job poster

Lekenzey Siddell

Recruiter @ Technical Link

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

ASIC Chip Lead / Design Engineer

Brooklyn Park, Minnesota

•

5d ago

Easy Apply

Full-time

145,000 - 205,000

PMIC Digital Design Engineer

Hybrid in Allen, Texas

•

4d ago

Easy Apply

Contract

60 - 90