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ASIC Engineering Technical Leader

PDDN Inc

San Jose, California • Today

Easy Apply

Full-time, Part-time, Contract, Third Party

ASIC Engineering Technical Leader

SDH Systems

California • Today

Full-time, Contract

Engineering Technical Leader - Systems

Wabtec

Grove City, Pennsylvania • Today

Full-time

USD 104,800.00 - 149,300.00 per year

Engineering Technical Leader - Systems

Wabtec

Pittsburgh, Pennsylvania • Today

Full-time

USD 104,800.00 - 149,300.00 per year

Engineering Technical Leader - Systems

Wabtec

Erie, Pennsylvania • Today

Full-time

USD 104,800.00 - 149,300.00 per year

Engineering Technical Leader - Process

Kimberly-Clark

Chester, Pennsylvania • Today

Full-time

USD 140,320.00 - 173,360.00 per year

Senior Process Engineering Technical Leader

Micron Technology Inc

Boise, Idaho • Today

Full-time

Engineering Technical Leader - Network Systems

Wabtec

Erie, Pennsylvania • Today

Full-time

USD 91,000.00 - 129,800.00 per year

ASIC Validation Lead/Engineering Manager

Metalight Solutions Inc

Sunnyvale, California • Yesterday

Easy Apply

Contract

Depends on Experience

Technical Leader - Project Engineering

GE Vernova

Greenville, South Carolina • Today

Full-time

USD 113,200.00 - 188,800.00 per year

2027 Masters ASIC Package Engineering Co-op/Intern

AMD (Advanced Micro Devices)

Santa Clara, California • Today

Full-time

USD 104,000.00 per year

2027 Undergrad ASIC Package Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 66,560.00 per year

2027 Masters ASIC Package Engineering Co-op/Intern

AMD (Advanced Micro Devices)

Austin, Texas • Today

Full-time

USD 99,840.00 per year

2027 Undergrad ASIC Package Engineering Co-op/Intern

AMD (Advanced Micro Devices)

Austin, Texas • Today

Full-time

USD 60,320.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX

Austin, Texas • Today

Full-time

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX

Palo Alto, California • Today

Full-time

USD 135,000.00 - 175,000.00 per year

Senior Engineer, Physical Design Engineering (ASIC)

Analog Devices, Inc.

New Jersey • Today

Full-time

USD 116,960.00 - 160,820.00 per year

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX

Irvine, California • Today

Full-time

USD 125,000.00 - 160,000.00 per year

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX

Redmond, Washington • Today

Full-time

USD 125,000.00 - 165,000.00 per year

Engineering Intern - AI/ML ASIC CAD (Spring 2027 Co-Op)

Rivian

Palo Alto, California • Today

Full-time

USD 45.00 - 51.00 per hour

Building Automation Systems (BAS) Technical Leader

Jobot

Grapevine, Texas • Today

Full-time

USD 125,000.00 - 150,000.00 per year

Technical Leader -Multiple openings

Altimetrik

Cincinnati, Ohio • Today

Easy Apply

Full-time

Depends on Experience

Space Systems Engineering Leader

Aerospace Corporation

Patterson, Ohio • Today

Full-time

USD 120,800.00 - 181,100.00 per year

Engineering Project Leader

Clarios

Milwaukee, Wisconsin • Today

Full-time

Process Engineering Team Leader

Lincoln Property Company

Alvin, Texas • Today

Full-time

USD 160,000.00 - 200,000.00 per year

Automation Engineering Leader

Howmet Aerospace

Whitehall, Michigan • Today

Full-time

Emerging Leader Engineering

Sonoco Products Company

Horsham, Pennsylvania • Today

Full-time

USD 68,000.00 - 71,000.00 per year

AI Engineering Leader

Vertafore

Denver, Colorado • Today

Full-time

USD 200,000.00 - 300,000.00 per year

Global Systems Engineering Leader, SRC

Philips North America

Murrysville, Pennsylvania • Today

Full-time

USD 204,750.00 - 327,600.00 per year

Plant Engineering Leader

Owens Corning

Kansas City, Kansas • Today

Full-time

Job Details

Skills

RTL Design
Verilog
DFT
Python
C++
Logic Analyzer
Memory Controllers
Validation

Summary

Role: ASIC Engineering Technical Leader

Location: San Jose, CA (Onsite)

Start Date: Immediate

Type: Contract (C2C/W2)

Interview: Phone/Video

We are seeking an ASIC Engineering Technical Leader with strong expertise in DesignforTest (DFT) for nextgen optical communication ASICs. Responsibilities include DFT architecture implementation, scan insertion, ATPG pattern generation, silicon debug, integration/verification of DFT fabrics, gatelevel simulations, and automation using Python/Tcl/C++.

Qualifications:

BS + 8 yrs / MS + 6 yrs / PhD + 3 yrs experience
Proven background in ASICs, DFT setup, scan insertion, and validation
Handson with Siemens Tessent, ATPG, Memory/Logic BIST
Strong scripting (Python/Tcl/C++) and RTL debugging skills

Preferred:

10+ yrs ASIC/DFT experience, SSN expertise, ATE tester exposure
Verilog/SystemVerilog integration, advanced silicon process knowledge

Gaurav

PDDN Inc., Fremont, CA

Phone:

Email:

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10202969
Position Id: PN- 4419-3421-1790371637
Posted 14 days ago

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San Jose, California

•

2d ago

Design for Test (DFT) Engineer Location: San Jose, CA Duration: 12 + Months (Potential Extension) Interview Process: Virtual/Onsite Rate: Up to $130/hr on W2 (No Benefits) Job OverviewWe are seeking an experienced Design for Test (DFT) Engineer to support the development and validation of next-generation semiconductor products. The role involves close collaboration with Front-End Design and Physical Design teams to implement and optimize DFT solutions for advanced wireless and connectivity c

Easy Apply

Contract

100 - 130

DFT Lead Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT spe

Full-time

USD 143,800.00 - 230,000.00 per year

DFT Engineer

San Jose, California

•

16d ago

DFT EngineerIntroduction:The DFT Engineer position at Sivaltech Inc involves working on ASIC/SoC designs, implementing Design for Testability (DFT) techniques, and ensuring the efficient testing of semiconductor devices. The role requires expertise in DFT tools, verification, testing, and debugging to support the overall product development lifecycle. Responsibilities:Implement DFT strategies for ASIC/SoC designsWork on Scan, JTAG, BIST, and MBIST techniquesGenerate test patterns and verify DFT

Easy Apply

Third Party, Contract

Depends on Experience

DFT Engineers

Santa Clara, California

•

Yesterday

Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock verification conceptsStrong grasp of digital design

Easy Apply

Full-time