About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on LinkedIn and X.
Senior Engineer, Process Sustaining Engineering in Yield/Integration areas: Provides technical and sustaining engineering support in a manufacturing area. Yield Improvement for Fab Electrical Test and Probe Parametric Test for Bipolar, CMOS , DMOS, RF and BICMOS products and technologies. Propose and implement process changes for improved yield or to facilitate fab modernization. Qualify new products and review process changes and new tool qualification for improved resiliency. Bring up newly added testers and qualify for production and setup data transfer and report. Test time reduction by reducing redundancy tests and using sampling method to improve test efficiency and improve test capacity. Develops and conducts statistical analysis such as Design of Experiments (DOE) and Statistical Process Control (SPC) targeting physical cause of failure for yield loss and improving quality. Interacts with product design and development personnel to ensure that processes and designs are compatible.
Requirements:
- Bachelors or Masters degree in ChemE, Mat Sci, EE, Physics, Chemistry or a related discipline.
- 4+ years of direct semiconductor industry experience with Yield improvement and Integration process.
- Advanced understanding of statistical process control (SPC) and engineering statistics.
- Excellent written, verbal, and presentation skills. Applicants must be able to train, influence, and motivate coworkers with educations ranging from GED to PhD and experience ranging from new hire to SVP.
- Ability to drive best in class quality, productivity, throughput, environmental performance, process robustness, cost, and manufacturability within own organization.
- Analyze Electrical test and Sort Yield data to identify key issues across a broad range of areas and effectively communicate recommendations to cross-functional teams
- Drive solution development, change management, and monitor effectiveness of any new process implementation or changes.
- Responsible to prepare, analyze and present key operational metrics, performance against targets and trends to senior management, including improvement recommendations and solutions
- Coordinate and collaborate with key groups like IT, Supply Chain Management, Process Engineering and other site support groups to meet internal and external customer demand
- Partner directly with manufacturing modules to optimize production for bottleneck toolsets and drive projects to increase efficiency
- Good understanding of device Physics, process integration knowledge and testing methodology to manage any process excursion and recommending material disposition.
- Knowledge of device layout, design and circuit analysis to identify weakness of the process and recommending innovative process improvement
- Recommend failure analysis method for Electrical and sort yield performance issue
- Fab SPC process control and aligning inline process control specs to Electrical parameter specs
- Interface with Product Engineering and Quality Assurance for qualification of new products, new processes, and process changes.
Preferred:
- 4+ years of direct semiconductor industry experience in yield improvement and process integration areas.
- Experience in WAT/ETEST with HP/Keysight tester, Keithley tester an advantage.
- Significant knowledge of device physics as-well-as bipolar and MOS device integration.
- Strong data analysis skills, and knowledge of various failure analysis methods
- Advanced statistics, problem solving mindset, SQL, C++, Exensio Data Analytic Software tool, KLA Klarity ACE analytic software tool
- Able to occasionally travel domestically and internationally as needed.
- Excellent organizational skills to manage multiple projects across geographically disbursed teams
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except s, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: No
Shift Type: 1st Shift/Days
The expected wage range for a new hire into this position is $95,600 to $131,450.
- Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
- This position qualifies for a discretionary performance-based bonus which is based on personal and company factors
- This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
- Benefits for the position includes 10 paid holidays per year, paid vacation starting at 136 hours per year for full-time employees (prorated for part-time employees), and paid sick time that exceeds the requirements of the Washington State Sick Leave law.
